PR0	=: ^O<0*40>
PR1	=: ^O<1*40>
PR2	=: ^O<2*40>
PR3	=: ^O<3*40>
PR4	=: ^O<4*40>
PR5	=: ^O<5*40>
PR6	=: ^O<6*40>
PR7	=: ^O<7*40>

V.TR4	=: ^O<  4>
V.TR10	=: ^O< 10>
V.BPT	=: ^O< 14>
V.IOT	=: ^O< 20>
V.PWFL	=: ^O< 24>
V.EMT	=: ^O< 30>
V.TRAP	=: ^O< 34>
V.MMU	=: ^O<250>

; MMU

SSR0 	=: ^O<177572>	; SSR0 Control and status
;   15      Non-resident
;   14      Length
;   13      Read-only
;   12      Trap
;   11 - 10 Unused
;    9      Enable Trap
;    8      Maintenance
;    7      Instruction Completed
;    6 -  5 CPU Mode
;    4      I/D
;    3 -  1 Page
;    0 -    Enable
	MM0.EN	=: ^O<1>

SSR1	=: ^O<177574>	; SSR1 Register increment/descrement record
;  15 - 11 Change
;  10 -  8 Register
;   7 -  3 Change
;   2    0 Register

SSR2	=: ^O<177576>	; Virtual address associated with the fault (usually the instruction address)

SSR3	=: ^O<172516>	; D-space enable/disable (per mode)
;   15 -  6 Unused
;    5      Enable UNIBUS Map
;    4      Enable 22-bit
	MM3.22	=: ^O<20>
;    3      Unused
;    2      Kernel
;    1      Supervisor
;    0      User
; PDR
;   15      Don't Cache
;   14 -  8 Length
;    7      Trapped
;    6      Written
;    5 -  4 Unused
;    3      Direction
;    2 -  0 Access Control
;             0 Non-resident           - abort all accesses
;             1 Read-only watched      - abort on write, trap on read
;             2 Read-only              - abort on write
;             3 Unused, reserved       - abort all accesses
;             4 Read/write all watched - trap on read or write
;             5 Read/write watched     - trap on write
;             6 Read/write             - none
;             7 Unused, reserved       - abort all accesses
	P.NCH	=: ^O<100000>
	P.LNM	=: ^O<177>*^O<400>
	P.AA2	=: ^O<7>	; 111 abort all accesses
	P.RW	=: ^O<6>	; 110 none
	P.RWT	=: ^O<5>	; 101 trap on write
	P.AT	=: ^O<4>	; 100 trap on read or write
	P.AA1	=: ^O<3>	; 011 abort all accesses
	P.RWA	=: ^O<2>	; 010 abort on write
	P.RTWA	=: ^O<1>        ; 001 abort on write, trap on read
	P.NONE	=: ^O<0>        ; 000 abort all accesses

SISDR0	=: ^O<172200> ; 172200 - 172216 SISDx Supervisor I-Space PDR #x
SISDR1	=: ^O<172202>
SISDR2	=: ^O<172204>
SISDR3	=: ^O<172206>
SISDR4	=: ^O<172210>
SISDR5	=: ^O<172212>
SISDR6	=: ^O<172214>
SISDR7	=: ^O<172216>

SDSDR0	=: ^O<172220> ; 172220 - 172236 SDSDx Supervisor D-Space PDR #x
SDSDR1	=: ^O<172222>
SDSDR2	=: ^O<172224>
SDSDR3	=: ^O<172226>
SDSDR4	=: ^O<172230>
SDSDR5	=: ^O<172232>
SDSDR6	=: ^O<172234>
SDSDR7	=: ^O<172236>

SISAR0	=: ^O<172240> ; 172240 - 172256 SISAx Supervisor I-Space PAR #x
SISAR1	=: ^O<172242>
SISAR2	=: ^O<172244>
SISAR3	=: ^O<172246>
SISAR4	=: ^O<172250>
SISAR5	=: ^O<172252>
SISAR6	=: ^O<172254>
SISAR7	=: ^O<172256>

SDSAR0	=: ^O<172260> ; 172260 - 172276 SDSAx Supervisor D-Space PAR #x
SDSAR1	=: ^O<172262>
SDSAR2	=: ^O<172264>
SDSAR3	=: ^O<172266>
SDSAR4	=: ^O<172270>
SDSAR5	=: ^O<172272>
SDSAR6	=: ^O<172274>
SDSAR7	=: ^O<172276>

KISDR0	=: ^O<172300> ; 172300 - 172316 KISDx Kernel     I-Space PDR #x
KISDR1	=: ^O<172302>
KISDR2	=: ^O<172304>
KISDR3	=: ^O<172306>
KISDR4	=: ^O<172310>
KISDR5	=: ^O<172312>
KISDR6	=: ^O<172314>
KISDR7	=: ^O<172316>

KDSDR0	=: ^O<172320> ; 172320 - 172336 KDSDx Kernel     D-Space PDR #x
KDSDR1	=: ^O<172322>
KDSDR2	=: ^O<172324>
KDSDR3	=: ^O<172326>
KDSDR4	=: ^O<172330>
KDSDR5	=: ^O<172332>
KDSDR6	=: ^O<172334>
KDSDR7	=: ^O<172336>

KISAR0	=: ^O<172340> ; 172340 - 172356 KISAx Kernel     I-Space PAR #x
KISAR1	=: ^O<172342>
KISAR2	=: ^O<172344>
KISAR3	=: ^O<172346>
KISAR4	=: ^O<172350>
KISAR5	=: ^O<172352>
KISAR6	=: ^O<172354>
KISAR7	=: ^O<172356>

KDSAR0	=: ^O<172360> ; 172360 - 172376 KDSAx Kernel     D-Space PAR #x
KDSAR1	=: ^O<172362>
KDSAR2	=: ^O<172364>
KDSAR3	=: ^O<172366>
KDSAR4	=: ^O<172370>
KDSAR5	=: ^O<172372>
KDSAR6	=: ^O<172374>
KDSAR7	=: ^O<172376>
                
UISDR0	=: ^O<177600> ; 177600 - 177616 UISDx User       I-Space PDR #x
UISDR1	=: ^O<177602>
UISDR2	=: ^O<177604>
UISDR3	=: ^O<177606>
UISDR4	=: ^O<177610>
UISDR5	=: ^O<177612>
UISDR6	=: ^O<177614>
UISDR7	=: ^O<177616>
UDSDR0	=: ^O<177620> ; 177620 - 177636 UDSDx User       D-Space PDR #x
UDSDR1	=: ^O<177622>
UDSDR2	=: ^O<177624>
UDSDR3	=: ^O<177626>
UDSDR4	=: ^O<177630>
UDSDR5	=: ^O<177632>
UDSDR6	=: ^O<177634>
UDSDR7	=: ^O<177636>
UISAR0	=: ^O<177640> ; 177640 - 177656 UISAx User       I-Space PAR #x
UISAR1	=: ^O<177642>
UISAR2	=: ^O<177644>
UISAR3	=: ^O<177646>
UISAR4	=: ^O<177650>
UISAR5	=: ^O<177652>
UISAR6	=: ^O<177654>
UISAR7	=: ^O<177656>
UDSAR0	=: ^O<177660> ; 177660 - 177676 UDSAx User       D-Space PAR #x
UDSAR1	=: ^O<177662>
UDSAR2	=: ^O<177664>
UDSAR3	=: ^O<177666>
UDSAR4	=: ^O<177670>
UDSAR5	=: ^O<177672>
UDSAR6	=: ^O<177674>
UDSAR7	=: ^O<177676>

PARH2	=: ^O<172512>

N$WNDW	=: ^O<100000>		; Базовый адрес окна доступа ко всей памяти в HALT режиме

;

PS	=: ^O<177776>

;
; Вектора регистры устройств
;

; Clock

V.LTC	=: ^O<100>

; Консольный терминал

V.TKB	=: ^O< 60>
V.TPS	=: ^O< 64>

TKS	=: ^O<177560>
TKB	=: ^O<177562>
TPS	=: ^O<177564>
TPB	=: ^O<177566>

; Line printer

LPS	=: ^O<177514>
LPB	=: ^O<177516>