QKDA - 11/60 basic CPU test ABSTRACT: This tests are partitioned into four sections: 1. basic CPU test to verify the "hardcore". Any fault causes the program to halt. 2. basic instruction test, any error causes a halt. 3. comprehensive instruction test (main program) tests all instructions and reports any errors. 4. tests instructions in various combinations manipulating variable data patterns. It also tests the MED and ERROR LOGGING features of the CPU. HARDWARE REQUIREMENTS: The test needs 16k words, a DL11-W line clock and a terminal. OPERATING PROCEDURES: 200 normal start SWITCH SETTINGS: SW 15 =1 halt on error SW 14 =1 loop on the current test SW 13 =1 inhibit normal error printouts SW 12 =1 inhibit all error printouts SW 11 =1 inhibit subtest interactions SW 10 =1 search for and continuously loop on the test number selected by SW 08-00 Only for test #176 - #767 since the scope utility is not active until test #176 . NOTES: QKDAA0. 1. the test would not recover from a power fail correctly between test 166 & 176 2. a MED instr in user mode did not cause a trap causing an error in subtest 756 QKDAB0. If "battery discharged" signal goes low between power down and power up, bit 9 in log/jam reg. goes low on power up. This causes test to fail at loc 57362: "TIMEOUT BIT NOT SET IN CPU ERR REG OR LOG JAM". QKDAC0. hardware ECO M7877-002 has corrected previous problem with bit 9 in log/jam reg. This change requires test 762 to check bit 9 to be set. QKDAD0. Test assumes PSW clear when starting. This is not so and false errors are detected. QKDB - 11/60 CPU Trap test ABSTRACT: This program checks that on all trap operations register 6 is decremented the correct amount, that the correct PC is saved on the stack, that the old condition codes and priority are placed on the stack and that the new status and condition codes are correct. Both the "TRAP" and "EMT" trap instructions are tested to see that all combinations will trap. Checked also is that all restricted instructions will trap. Verification of the "TRT" instruction 000003 which is used for software debug routines (ODT, DDT) is done. Also the trace bit is tested. Stack overflow, yellow and red zone violation are checked. OPERATING PROCEDURES: 200 normal start The program prints the title and starts testing. ERROR REPORTING: If an error is detected, there will be a halt. In this case register 6 (the stackpointer) should be examined to determine its contents. Memory as specified by R6 contains the PC + 2 of the failing instruction which caused the faulty trap or interrupt. SWITCH SETTINGS: none NOTES:none QKDC - 11/60 instruction I/O exer ABSTRACT: This is an overall test of the 11/60 CPU, MEMORY MANAGEMENT in USER and KERNEL mode and up to 124k words of memory. It executes each instruction in all address modes and includes tests for Traps, Interrupts, Floating Point, the UNIBUS and the MASSBUS. It is using peripherals like a RK11-RK05, for relocating the program. The low byte of the display register contains the current test #, the upper byte displays bits 11:4 of KERNEL PAR0 (correspond to bits 17:10 physical address). Power fail is supported (only R0-R6 & SW is saved). OPERATING PROCEDURES: *** TAKE CARE TEST WILL *** *** WRITE ONTO THE DISK *** Set the switches Load address 200 and start ERROR REPORTING: Detailed error reports are printed out. SWITCH SETTINGS: SW 15 =1 halt on error SW 14 =1 loop on the current subtest SW 13 =1 inhibit error printouts SW 12 =1 inhibit use of UNIBUS EXERCISER SW 11 =1 inhibit subtest interations SW 10 =1 ring bell on error SW 09 =1 loop on first failure (even if the failure is intermittend) SW 08 =1 relocate with CPU (no disk needed) SW 07 =1 inhibit system size typeout SW 06 =1 inhibit relocation SW 05 =1 inhibit round robin (use only selected disk rather all available disks) SW 04 =1 inhibit random disk address (use start address 0 of the disk) SW 03 =1 inhibit use of MASSBUS TESTER SW 02 SW 2,1,0 along with SW 05 selects a disk SW 01 for relocating the program SW 00 binary 0 = RP11 / RP03 + SW 05 1 = RK11 / RK05 + SW 05 4 = RH11 / RP04 + SW 05 5 = RH11 / RS03/04 + SW 05 Test will write the disk and Unit# which will be used for relocation (SW 07 =1) and waits for the operator to type a character (allows to write protect disks). NOTES: Nothing QKKA - 11/60 cache test ABSTRACT: It is a 13k word program, but 124k words are needed for complete check of the cache TAG field. Also needed is a NPR device for testing invalidation of cache locations during NPR's DATO's (SW 08 =1). The choice is : UNIBUS exerciser, RK05, RP03 or TU10. When SW 08 is set the test will request you to select one of these devices. Before any device is choosen, it should be powered up, write enabled (scratch media loaded) and in the ready state. The program will then ask you device specific questions. The diagnostic checks the cache data path as well as the cache RAM chips with several data patterns. When SW 07 is set the program will ask you to switch off the machine and on again. The test will check the initialization (clear) of the cache. OPERATING PROCEDURES: Set the switches Load address 200 and start ERROR REPORTING: There are 2 types of errors: 1. "FATAL ERROR" is a catastrophic failure which would cause all further printouts to be wrong or misleading. 2. "ERROR" the contents of the error report identifies the hardware under test at the time of the failure. Other information such as cache control fields and failing addresses are also reported. SWITCH SETTINGS: SW 15 =1 halt on error SW 14 =1 loop on the current test SW 13 =1 inhibit error typeouts SW 12 =1 bypass tests using Memory Management SW 11 =1 inhibit subtest interations SW 10 =1 ring bell on error SW 09 =1 loop on error SW 08 =1 enable NPR device tests SW 07 =1 enable power up test NOTES: Nothing QFPA - FP11-E Floating Point part 1 ABSTRACT: This is the FP-UNIT (HOT and WARM) basic logic test. When the program is started a message is printed indicating the presence/absence of an optional FP11-E HOT floating point unit. (based upon the "WHAMI-REG" bit 4 (CPU internal register can only be addressed by the maintenance instruction MED 076600). The program selects HOT or WARM-FP by setting and clearing bit 12 of the LOG FLAG/INTERRUPT REG. (select HOT-FP = 1, SELECT WARM-FP = 0) It supports power fail, but none of the FP11 registers are saved. This can result in a error message typed after power is restored. SOFTWARE: The test assumes CPU, CACHE, and MEMORY are OK! OPERATING PROCEDURES: 200 normal start The program prints its name and starts testing. ERROR REPORTING: In the first line of the error message is indicated whether the error happened in the HOT or WARM FP11. (the warm-fp11 is integrated in the CPU, the hot-fp11 consists of modules M7878, M7879, M7880, M7881). SWITCH SETTINGS: SW 15 =1 halt on error SW 14 =1 loop on current test SW 13 =1 inhibit error typeouts SW 12 =1 inhibit "END PASS ...." typeouts SW 11 =1 inhibit iterations SW 10 =1 ring bell on error SW 09 =1 loop on error SW 07 =1 print error summary (ignore SW 13) SW 01 =0 HOT-FP / WARM-FP alternately each pass (i.e. PASS#1 HOT-FP , PASS#1 WARM-FP, PASS#2 HOT-FP , PASS#2 WARM-FP ) SW 01 =1 test only until specified in SW 00 SW 00 =1 test WARM-FP if SW 01 is set SW 00 =0 test HOT-FP if SW 01 is set NOTES : QFPAA0. Program does not properly terminate between hot and warm floating point units if both are enabled and iterations are allowed. QFPB - FP11-E Floating Point part 2 ABSTRACT: This is the FP-UNIT (HOT and WARM) advanced instruction test. When the program is started a message is printed indicating the presence/absence of an optional FP11-E HOT floating point unit. (based upon the "WHAMI-REG" bit 4 (CPU internal register can only be addressed by the maintenance instruction MED 076600). The program selects HOT or WARM-FP by setting and clearing bit 12 of the LOG FLAG/INTERRUPT REG. (HOT-FP = 1, SELECT WARM-FP = 0) It supports power fail, but none of the FP11 registers are saved. This can result in a error message typed after power is restored. SOFTWARE: The test assumes basic CPU, CACHE, and MEMORY are OK! Run the tests in sequence first part 1 then 2,3,4,5 OPERATING PROCEDURES: 200 normal start The program prints its name and starts testing. ERROR REPORTING: In the first line of the error message is indicated whether the error happened in the HOT or WARM FP11. (the warm-fp11 is integrated in the CPU, the hot-fp11 consists of modules M7878, M7879, M7880, M7881). SWITCH SETTINGS: SW 15 =1 halt on error SW 14 =1 loop on current test SW 13 =1 inhibit error typeouts SW 12 =1 inhibit "END PASS ...." typeouts SW 11 =1 inhibit iterations SW 10 =1 ring bell on error SW 09 =1 loop on error SW 07 =1 print error summary (ignore SW 13) SW 01 =0 HOT-FP / WARM-FP alternately each pass (i.e. PASS#1 HOT-FP , PASS#1 WARM-FP, PASS#2 HOT-FP , PASS#2 WARM-FP ) SW 01 =1 test only until specified in SW 00 SW 00 =1 test WARM-FP if SW 01 is set SW 00 =0 test HOT-FP if SW 01 is set NOTES: QFPBA0. Program does not properly terminate between hot and warm floating point units if both are enabled and iterations are allowed. QFPC - FP11-E Floating Point part 3 ABSTRACT: The program selects HOT or WARM-FP by setting and clearing bit 12 of the LOG FLAG/INTERRUPT REG. (HOT-FP = 1, SELECT WARM-FP = 0) The test is using the DL11-W line clock to provide I/O interrupts during execution. If present the KW11-P programmable clock will also be utilized. It supports power fail, but none of the FP11 registers are saved. This can result in a error message typed after power is restored.\ SOFTWARE: The test assumes basic CPU, CACHE, and MEMORY are OK! Run the tests in sequence first part 1 then 2,3,4,5 OPERATING PROCEDURES: 200 normal start The program prints its name and starts testing. ERROR REPORTING: In the first line of the error message is indicated whether the error happened in the HOT or WARM FP11. (the warm-fp11 is integrated in the CPU, the hot-fp11 consists of modules M7878, M7879, M7880, M7881). SWITCH SETTINGS: SW 15 =1 halt on error SW 14 =1 loop on current test SW 13 =1 inhibit error typeouts SW 12 =1 inhibit "END PASS ...." typeouts SW 11 =1 inhibit iterations SW 10 =1 ring bell on error SW 09 =1 loop on error SW 07 =1 print error summary (ignore SW 13) SW 01 =0 HOT-FP / WARM-FP alternately each pass (i.e. PASS#1 HOT-FP , PASS#1 WARM-FP, PASS#2 HOT-FP , PASS#2 WARM-FP ) SW 01 =1 test only until specified in SW 00 SW 00 =1 test WARM-FP if SW 01 is set SW 00 =0 test HOT-FP if SW 01 is set NOTES: QFPCA0. The HOT-FP microbreak register is uninitialized at power up and causes traps when maintenance mode is entered. HOT-FP service is not honored at priority 7 until next FP instruction. Pending service condition is lost. Program does not properly alternate between hot and warm floating point units if both are enabled and iterations are allowed. QFPD - FP11-E Floating Point part 4 ABSTRACT: This is the FP-UNIT ADD/SUB/MUL/DIV random exerciser. The program selects HOT or WARM-FP by setting and clearing bit 12 of the LOG FLAG/INTERRUPT REG. (HOT-FP = 1, SELECT WARM-FP = 0) It supports power fail, but none of the FP11 registers are saved. This can result in a error message typed after power is restored. SOFTWARE: The test assumes basic CPU, CACHE, and MEMORY are OK! Run the tests in sequence first part 1 then 2,3,4,5 OPERATING PROCEDURES: 200 normal start The program prints its name and starts testing. ERROR REPORTING: In the first line of the error message is indicated whether the error happened in the HOT or WARM FP11. (the warm-fp11 is integrated in the CPU, the hot-fp11 consists of modules M7878, M7879, M7880, M7881). SWITCH SETTINGS: SW 15 =1 halt on error SW 14 =1 loop on current test SW 13 =1 inhibit error typeouts SW 12 =1 inhibit "END PASS ...." typeouts SW 11 =1 inhibit iterations SW 10 =1 ring bell on error SW 09 =1 loop on error SW 07 =1 print error summary (ignore SW 13) SW 01 =0 HOT-FP / WARM-FP alternately each pass (i.e. PASS#1 HOT-FP , PASS#1 WARM-FP, PASS#2 HOT-FP , PASS#2 WARM-FP ) SW 01 =1 test only until specified in SW 00 SW 00 =1 test WARM-FP if SW 01 is set SW 00 =0 test HOT-FP if SW 01 is set NOTES: QFPDA0. Program does not properly alternate between hot and warm floating point units if both are enabled and iterations are allowed. QFPE - FP11-E Floating Point part 5 ABSTRACT: This program tests HOT-FP-E only and assumes the CPU, CACHE, MEMORY and WARM-FP (standard in the CPU) is running faultless. It supports power fail, but none of the FP11 registers are saved. This can result in a error message typed after power is restored. It tests: 1. base processor specific 2. base processor / FP11-E interface 3. FP11-E instr. decode, sequencing contr. 4. FP11-E exponent datapath / control 5. FP11-E fraction datapath / control 6. FP11-E ROM multiplier datapath / contr. 7. FP11-E exception conditions 8. FP11-E maintenance instructions HARDWARE REQUIREMENTS: The test requires 16k words of any type of memory (core / MOS), a DL11-W line clock and a HOT-FP-E. OPERATING PROCEDURES: 200 normal start The program prints its name and starts testing. ERROR REPORTING: This diagnostic is oriented towards the specific hardware architecture of the CPU and the FP11-E. To this end hardware information is included within each test header (listing or microfiche) on a module by module basis. SWITCH SETTINGS: SW 15 =1 halt on error SW 14 =1 loop on current test SW 13 =1 inhibit error typeouts SW 12 =1 inhibit "END PASS ...." typeouts SW 11 =1 inhibit iterations SW 10 =1 ring bell on error SW 09 =1 loop on error SW 07 =1 16 bit FP data typeouts =0 sign/exp/frac FP data typeouts SW 06 =1 summary only error printouts SW 05 =1 if error occurs and loop on error (SW 09) is set, forces a tight-loop-on-error. NOTES: nothing