KKAA - 11/44 CPU and EIS test ABSTRACT: It checks all of the processor logic and microcode for all basic 11/44 instructions except the TRAP, and memory management instructions. The test does not check RTT, RTI, WAIT, RESET, TRAP, EMT instructions. To give you an idea what is tested : . all branches on the condition codes . tests internal data path (Unibus data transceivers and AMUX) with different data patterns . tests all scratch pad registers (GPR's) . tests the PSW, write into and read it back . tests all possible address modes . tests all instructions specified above . tests the EIS instructions ASH, ASCH, MUL, DIV HARDWARE REQUIREMENTS: The test needs 16k of memory. SOFTWARE: To check the full PDP-11/44 CPU run: - KKABC0 Trap test - KKACC0 Power fail test - KKTAB0 Memory management test part 1 - KKTBC0 Memory management test part 2 - KKUAC0 UBI MAP test - KKKAC0 Cache test - ZDLDF0 MFU SLU test - KKAAB0 CPU and EIS test OPERATING PROCEDURES: LOAD ADDRESS 200 START The program does not print any title. After testing it prints repeatably: "END OF CKKAAA0 11/44 CPU/EIS" The diagnostic responds to the detection of all errors by storing certain information in memory and halting the processor. This information can be used by the operator to identify the error. For more information refer to your microfiche library. SWITCH SETTINGS: None. NOTES: KKAAA0.BIC Bit 0 of CPU errror reg not checked. Random Control Q not checked. KKAB - 11/44 CPU trap test ABSTRACT: This tests all operations and instructions that cause traps. Also tested are trap overflow conditions oddities of register 6, interrupts, the reset and wait instructions. This is a series of instructions designed to detect and isolate also unexpected Traps and Interrupts. If a halt occurs register 6 (the stackpointer) should be examined to determine its contents. When the interrupt or trap occurred, memory as specified by R6 contains the PC of the instruction following the instruction which caused the faulty trap or interrupt. To give you an idea what is tested: . tests R6 (increment and decrement) . tests that a trap occurs on a reserved instruction . tests that correct PC and PSW is saved on the stack . tests all combinations of traps . tests IOT and EMT instructions . tests the TRACE-TRAP sequence . tests that a trap occurs on a non-existent address . tests that a decrement R6 to a value below 400 traps . tests that a TTY interrupt can cause on overflow trap . tests that a RESET goes to the outside world (UNIBUS) . tests the WAIT instruction (with the TTY) . tests the HALT instruction in Super and User mode . tests the PIR (Programmable Interrupt Request) HARDWARE REQUIREMENTS: The test needs 8k of memory. OPERATING PROCEDURES: 200 normal start 210 restart with pass count back to zero After testing it prints: "END OF CKKABA0 11/44 TRAPS" All errors will cause a CPU halt. SWITCH SETTINGS: None. NOTES: KKABA0.BIC Power monitor bit not checked. Random Control Q not checked. KKAC - 11/44 power fail test ABSTRACT: This tests is made of 11 subtests. The 2 milliseconds power down and power up time is checked on each power fail. The subtests check the following: . #01 simple down/up test in Kernel . #02 power fail with branch instruction . #03 power fail with EMT trap . #04 power fail with odd address . #05 power fail with time out in Kernel . #06 power fail with in the stack overflow (Kernel) . #07 power fail with reset . #10 power fail with memory management abort . #11 will use mem.managmt to run the volatile test for all memory available SOFTWARE: It is assumed that CPU, Traps, Memory Management, and UNIBUS MAP diagnostics have been run successfully. OPERATING PROCEDURES: 200 normal start It prints: "CKKACA0 11/44 POWER FAIL" "BOOT ENABLE SWITCH MUST BE OFF" Then it prints the size of the memory and operating instructions. The subtest number will be printed at the beginning of each test. Manually power down then up again for each subtest until the "END PASS" is printed. For MOS memory with no Battery-Backup use the STD BY (stand-by) mode. The program will identify the failing test and provide information on the error. After an error printout, the program will halt and return control to the console. SWITCH SETTINGS: Switch register bit 14 controls repeating of a failing subtest. This bit must be set to a 1 after error halt every time the test is to be operated. NOTES: KKACA0.BIC On power up, a subroutine previously loaded into PAR was found to be cleared. KKACB0.BIC Listing needs corrections. KKFB - 11/44 MFM multi function module - 8085 CPU test ABSTRACT: The Multi Function Module (MFM) self test is designed to test hardware associated with the 8085 FRONT-END CPU, handling the console functions on the 11/44. The T (Test) checks the 8085 Subsystem (CPU, ROM's, and RAM's). This test does not interfere with the state of the big CPU and the memory. After a successful pass it prints "CONSOLE". In addition, a LED on the MFM module will be turned on at the beginning of "T" and extinguished at the successful completion of "T". The "T" sequence is the following: . ROM checksum test . RAM data test . RAM address test The "T/E" sequence is the following: . all "T" basic tests . halt and continue test . PAX data line test . PAX address line test . console switch register test OPERATING PROCEDURES: >>>T[CR] Console self test command >>>T/E[CR] Console Extensive testing The test resides in the Console ROM's. An error would result in: >>>T/E[CR] CONSO ?8l ^C >>> "CONSOLE-TEST" is a progress message and some letters indicate the start of a new subtest: "C" 0 - 2k ROM test "O" 2 - 4k ROM test "NSO" console RAM data test "LE" testing done "-" halt continue test "T" data bus test "E" PAX address test "S" switch register test "T" test complete The failing test will be looped on unconditionally, exit from the loop is by control-C (^C). NOTES: *** (is not a MAIN-DEC program) KKKA - 11/44 cache test ABSTRACT: This test is running in only 16k. Optional a UNIBUS exerciser is used to test DMA transfers. At the start of the diagnostic, a small area of write control logic and the maintenance features are assumed to be working. The cache is completely turned off (no data is allowed to be cached out of the cache) and not turned on until 90 percent of the diagnostic is complete. The test is using memory management and the UNIBUS MAP. The following is tested: . cache registers, address select logic, AMR register . tests that the I/O page is not cached . tests the address path and TAG field with patterns . tests the cache bypass mode . tests that a DMA write invalidates cache (the UNIBUS exerciser is needed to perform the DMA's) . ........ and so on ........ OPERATING PROCEDURES: 200 normal start The program prints: CKKKAA0 11-44 KK11B CACHE To set the switches type ^P >>>D SW 100000 will set the bit 15 >>>C[CR] back to program I/O mode An error printout consists of a minimum of the failing subtest number and the location of the program where the error occurred. SWITCH SETTINGS: SW 15=1 halt on error SW 14=1 loop on test specified in SW 07 - SW 00 SW 13=1 inhibit error typeouts SW 11=1 inhibit iterations SW 09=1 loop on error SW 08=1 diag. will verify that invalidation will occur due to a read hit bypass condition. Test assumes physical strap W2 is in. SW 07-00 specifies subtest number for loop on test NOTES: KKKAA0.BIC "clear CCR" patch for REV A accidentally left out. KKKAB0.BIC Power monitor bit not being checked. KKTA - 11/44 memory management test (part 1) ABSTRACT: This is the memory management logic test 1, using a "bottom up" approach starting with the smallest segment and building up to cover all of the logic. This part does not test the special abort sequences, MFPI, MTPI, and CSM instructions. Run KKTBC0 after to test these instructions. Every other pass starting with the third one (3, 5, 7 ...) will exercise T-bit trapping unless it is inhibited. The test is able to handle power fails, but only R0 to R6 are saved. The test does the following: . the PSW, all PAR's and PDR's in Kernel . SUPERVISOR and USER mode in I & D space . the MMR0, MMR1, MMR2 and MMR3 by using different data patterns . the memory management in maintenance mode . 18 bit mapping, 22 bit mapping . the W-bit (written into page bit) OPERATING PROCEDURES: 200 normal start Set the desired Switch register : Type ^P >>>D SW 100000 will set the bit 15 >>>C[CR] back to program I/O mode It types the subtest number in which the error occurred, the PC where the error occurred and a verbal description of the error. SWITCH SETTINGS: These switches are rechecked periodically during testing. SW 15=1 halt CPU after error and error typeout SW 14=1 loop on subtest SW 13=1 inhibit printouts SW 12=1 inhibit trace trapping SW 10=1 bell on error SW 09=1 loop on error SW 08=1 loop on subtest in SW 07 - SW00 SW 07-00 specifies subtest number "Control-C" will cause the program to type the present test# and pass count, requests a new value for the switch register and starts with subtest 1 again. KKTB - 11/44 memory management test (part 2) ABSTRACT: This is the memory management logic test 2, complementing part 1. It tests the special abort sequences, MFPI, MTPI, and CSM instructions. Run KKTAB0 before this one. Every other pass starting with the third one (3, 5, 7 ...) will exercise T-bit trapping unless it is inhibited. The test is able to handle power fails. The test does the following: . the non-resident abort sequence . the read-only abort sequence . the page length abort sequence . the abort sequence in super/user mode . the instruction/data space abort . test the move from/to previous instructions . test the CSM (Call Supervisor Mode) instruction OPERATING PROCEDURES: 200 normal start Set the desired Switch register : Type ^P >>>D SW 100000 will set the bit 15 >>>C[CR] back to program I/O mode It types the subtest number in which the error occurred, the PC where the error occurred and a verbal description of the error. SWITCH SETTINGS: These switches are rechecked periodically during testing. SW 15=1 halt CPU after error and error typeout SW 14=1 loop on subtest SW 13=1 inhibit printouts SW 12=1 inhibit trace trapping SW 10=1 bell on error SW 09=1 loop on error SW 08=1 loop on subtest in SW 07 - SW00 SW 07-00 specifies subtest number "Control-C" will cause the program to type the present test# and pass number, requests a new value for the switch register and starts with subtest 1 again. NOTES: KKTBA0.BIC Diagnostic fails to test the CSM instruction. KKTBB0.BIC Test #3 fails with ECO #8 in. Power monitor bit 0 in CPU ERR reg not checked. KKUA - 11/44 UNIBUS Map test ABSTRACT: This program assumes the CPU, CACHE and Memory Management to be OK. This diagnostic will test the Unibus Mapping on the board M7098. The test does the following: . all map registers can be addressed . all map registers with a data pattern . addressing main memory through the UNIBUS (by relocating to top 128k and MAP disabled) . relocation via UNIBUS -UNIBUS MAP -MEMORY . the LMA register (last mapped address register) . UNIBUS memory when optionally selected by SW 05 =1 (test #31) OPERATING PROCEDURES: 200 normal start Set the desired Switch register : Type ^P >>>D SW 100000 will set the bit 15 >>>C[CR] back to program I/O mode It types the subtest number in which the error occurred, the PC where the error occurred and a verbal description of the error. SWITCH SETTINGS: SW 15=1 halt CPU after error and error typeout SW 14=1 loop on subtest SW 13=1 inhibit error printout SW 12=1 inhibit trace trapping SW 11=1 inhibit interactions SW 10=1 bell on error SW 09=1 loop on error SW 08=1 loop on subtest in SW 04 - SW00 SW 07=1 inhibit multiple error typeouts SW 05=1 test memory on the UNIBUS SW 04-00 select the subtest in case SW 08 is on There may be some cases where a bad cache module can interfere into this test and prohibits close isolation of an error. In this case you can run with the cache disabled. Simply load the cache control register (17777746) with 001000, then load 200 into R7 - >>>D/G 7 000200[CR], then >>>C (continue). The test will run normally except that certain tests will be skipped since the cache is disabled. Subtest #31 can test memory on the UNIBUS. NOTES: KKUAA0.BIC Does not test UBI MAP on 11/24 with and without memory. Power monitor bit not checked in CPU ERR reg. KFPA - 11/44 FP11-F test (part 1) ABSTRACT: This test is almost identical to the 11/34 FP11-A test. To test entire FP11-F run part 1, 2 and 3. Run the test in sequence (first part 1 then 2-3). Each other pass will exercise T-bit trapping starting with pass 3 the 5, 7, 9 ... unless SW 12 =1. The program prints the total number of passes completed and the total number of errors since the last end of pass message. This part 1 tests the more easy floating point instructions: LDFPS / STFPS load/store floating point status CFCC copy floating condition codes SETF / SETD set float. mode single/double precision SETI / SETL set integer/long integer mode STST store floating point exception and status LDF / LDD load floating single/double precision STD store floating point double precision number ADDF / ADDD add floating single/double precision numbers ADDD / SUBD add/subtract floating double precision numbers HARDWARE REQUIREMENTS: The test needs 15k of memory. OPERATING PROCEDURES: 200 normal start Set the desired Switch register: Type ^P >>>D SW 100000 will set the bit 15 >>>C[CR] back to program I/O mode SWITCH SETTINGS: SW 15=1 halt on error SW 14=1 loop on current test SW 13=1 inhibit error typeouts SW 12=1 inhibit T-bit trapping SW 11=1 inhibit interactions SW 10=1 ring bell on error SW 09=1 loop on error SW 08=1 loop on subtest specified in SW 06 - SW00 SW 07=1 print error summary (ignore SW 13) SW 06-00 selects subtest NOTES: KFPBA0.BIC Does not check power monitor bit in CPU ERR reg. KFPB - 11/44 FP11-F test (part 2) ABSTRACT: To test entire FP11-F run part 1, 2 and 3. Run the test in sequence (first part 1 then 2-3). The program prints the total number of passes completed and the total number of errors since the last end of pass message. This part 2 tests the following FP-11 - instructions: ADDF add floating single precision numbers ADDD add floating double precision numbers SUBD subtract floating double precision numbers CMPD compare floating single precision numbers CMPF compare floating double precision numbers DIVD divide floating single precision numbers DIVF divide floating double precision numbers MULD multiply floating single precision numbers MULF multiply floating double precision numbers MODD multiply and integerize floating single p. MODF multiply and integerize floating double p. Some long floating-point instructions can be interrupted (by BR from the UNIBUS) and started again (as if that instruction had never been started). This function can not be tested in the field. HARDWARE REQUIREMENTS: The test needs 15k of memory. OPERATING PROCEDURES: 200 normal start Set the desired Switch register: Type ^P >>>D SW 100000 will set the bit 15 >>>C[CR] back to program I/O mode SWITCH SETTINGS: SW 15=1 halt on error SW 14=1 loop on current test SW 13=1 inhibit error typeouts SW 12=1 inhibit T-bit trapping SW 11=1 inhibit interactions SW 10=1 ring bell on error SW 09=1 loop on error SW 08=1 loop on subtest specified in SW 06 - SW00 SW 07=1 print error summary SW 06-00 selects subtest NOTES: KFPBA0 Power monitor bit not checked in CPU ERR reg. KFPC - 11/44 FP11-F test (part 3) ABSTRACT: To test entire FP11-F run part 1, 2 and 3. Run the test in sequence (first part 1 then 2-3). The program prints the total number of passes completed and the total number of errors since the last end of pass message. Part 3 tests a lot of different floating point instructions, some of them with all possible source and destination modes. The results of the hardware floating point module is compared against the correct results written into the diagnostic. If Switch 12 =0 then each program will run with trace traps on every other pass. First pass will not enable trace traps. Switch 12 =1 disables T-bit trapping. Some long floating-point instructions can be interrupted (by BR from the UNIBUS) and started again (as if that instruction had never been started). This function can not be tested in the field. HARDWARE REQUIREMENTS: The test needs 15k of memory. OPERATING PROCEDURES: 200 normal start Set the desired Switch register : Type ^P >>>D SW 100000 will set the bit 15 >>>C[CR] back to program I/O mode SWITCH SETTINGS: SW 15=1 halt on error SW 14=1 loop on current test SW 13=1 inhibit error typeouts SW 12=1 inhibit T-bit trapping SW 11=1 inhibit interactions SW 10=1 ring bell on error SW 09=1 loop on error SW 08=1 loop on subtest specified in SW 06 - SW00 SW 07=1 print error summary SW 06-00 selects subtest NOTES: KFPCA0 The value of increment/decrement of the active register can be wrong. KFPCB0 Power monitor bit in CPU ERR reg not checked. ZKEE - 11/44 CIS test (also 11/23, 11/24) ABSTRACT: This program is not directed at any one CIS hardware implementation but rather is intended to provide an exersiser for all PDP-11 CIS processors. Therefore it can run also on a 11/23 or 11/24 having CIS option. It tests all CIS instructions in register and inline mode by using all combinations of operand data types, in USER, SUPER and KERNEL mode, memory management enabled/disabled, D-SPACE enabled/disabled and interrupts. Operands for each test case are either extracted from input tables or generated using a random number generator. Expected results are computed in the loop by emulating CIS instruction using basic PDP-11 instructions. HARDWARE REQUIREMENTS: The test needs 28k words of memory. OPERATING PROCEDURES: .R ZKEEC0 (200 normal start) start at 204 enter parameters manually start at 210 run quick verify mode only Starting at 204 will get you into a dialog mode: TEST INTERRUPTS IN CIS INSTR.(KW11 REQUIR.) (Y OR N)? INTR SOURCE (R=LTC,N=KW11-P @100KHZ, C=KW11-P @10KHZ.. RANDOM EXERCISE MODE (Y OR N) ? ENTER INSTRUCTION TO TEST CONTROL CHARACTERS: ^T : display test # and instruction under test ^C : restart exerciser (only when started in 204) ^D : display all operands and results . Continue ^E : same as ^D but query for continue ^O : print progress report ON/OFF toggle. SWITCH SETTINGS: Software switch register all zero for (28KW) worse case. SW 00 =1 program will query for test # (in decimal) to stop on and display. RUN TIME: With a normal start (at 200) it will do a quick verify pass, then a normal pass (about 30 minutes) followed by a random exerciser until the operator stops it. NOTES: ZKEEA0 does not run on a 11/23 and 11/24 ZKEEB0 CMPP instruction failed. ZDLH - 11/44 MFU-SLU & DL11-W test ??????????????