FKAA - 11/34 CPU test ABSTRACT: This program checks all of the processor logic and microcode for all basic 11/34 instructions except the TRAP, EIS and memory management instructions. The test does not check RTT, RTI, WAIT, TRAP, RESET, EMT instructions. To give you an idea what is tested: all branches on the condition codes tests internal data paths (Unibus data transceivers and AMUX) with different data patterns tests all scratch pad registers (GPR's) tests the PSW, write into and read it back tests all possible address modes tests all instructions specified above HARDWARE REQUIREMENTS: The test needs 8k of memory. SOFTWARE: To check the full 11/34 CPU run after: FKABD0 Trap test FKACA0 EIS test FKTGC0 Memory management test part 1 FKTHB0 Memory management test part 2 OPERATING PROCEDURES: .R FKAA?? (200 normal start) The program prints the title. After it prints END PASS repeatably. ERROR REPORTING: The diagnostic responds to the detection of all errors by storing certain information in memory and halting the processor. This information can be used by the operator to identify the error. For more information refer to your microfiche library. SWITCH SETTINGS: None. NOTES: FKAAA0.BIC Needs test to check out ECO M7266-00002 FKAAB0.BIC Is not chainable under XXDP+ monitor FKAB - 11/34 TRAP test ABSTRACT: This program tests all operations and instructions that cause traps. Also tested are trap overflow conditions oddities of register R6, interrupts, the reset and wait instructions. This is a series of instructions designed to detect and isolate unexpected Traps and Interrupts. If a halt occurs register R6 (the Stackpointer) should be examined to determine its contents. When the interrupt or trap occurred, memory as specified by R6 contains the PC of the instruction following the instruction which caused the faulty trap or interrupt. To give you an idea what is tested : tests R6 (increment and decrement) tests that a trap occurs on a reserved instruction tests that correct PC and PSW is saved on the stack tests all combinations of Traps tests IOT and EMT instructions tests the TRACE-TRAP sequence tests that a trap occurs on a nen-existent address tests that decrement R6 to a value below 400 traps tests that a TTY interrupt can cause an overflow trap tests that a RESET goes to the outside world (UNIBUS) tests the wait instruction (with the TTY) HARDWARE REQUIREMENTS: The test needs 4k of memory. OPERATING PROCEDURES: .R FKAB?? (200 normal start) 210 restart with pass count back to zero The program prints the title "CFKABD0 11/34 TRAPS TEST". After testing it prints "CFKABD0 11/34 TRAPS TST DONE". ERROR REPORTING: All errors will cause a CPU halt. SWITCH SETTINGS: None. NOTES: FKABB0.BIC Test #113 fails when FP11-A is installed. FKABC0.BIC Diagnostic does not print title. FKAC - 11/34 EIS test ABSTRACT: This program tests the ASH, ASHC, MUL, DIV instructions. In the memory locations 404 is a 16 bit pass count. This test can be power failed with no error. HARDWARE REQUIREMENTS: The test needs 4k of memory. OPERATING PROCEDURES: .R FKAC?? (200 normal start) 222 restart to save the pass count. The program does not print any title. After testing it prints "END PASS". ERROR REPORTING: The format is as follows: ADR ERRNM ADR = address of error ERRNM = error number In most cases the comment beside the call for halt subroutine tells what was being checked and what was expected. SWITCH SETTINGS: SW 15 = 1 halt on error SW 13 = 1 inhibit error type outs If no hardware switch register is available, the program automatically uses the contents of location 176 as the software switch register. FFPA - 11/34 FP11-A part 1 ABSTRACT: To test the entire FP11-A run part 1, 2 and 3. Run the tests in sequence (first part 1 then 2-3). If you have no hardware switch register type "control G" to change the switches. The program prints the total number of passes completed and the total number of errors since the last end of pass message. This part 1 tests the more easy floating point instructions: LDFPS load floating point status STFPS store floating point status CFCC copy floating condition codes SETF set floating mode (single precision) SETD set floating mode (double precision) SETI set integer mode SETL set long integer mode STST store floating point exception and status LDF load floating double precision LDD load floating number (single precision) STD store floating double precision number ADDF add floating single precision numbers ADDD add floating double precision numbers SUBD subtract floating double precision numbers OPERATING PROCEDURES: .R FFPA?? (200 normal start) The program prints its name, if there is no physical console it will ask for Switches = xxxxxx SWITCH SETTINGS: SW 15 = 1 halt on error SW 14 = 1 loop on current test SW 13 = 1 inhibit error typeouts SW 12 = 1 inhibit T-bit trapping SW 11 = 1 inhibit iterations SW 10 = 1 ring bell on error SW 09 = 1 loop on error SW 08 = 1 loop on subtest specified in SW 06 - 00 SW 07 = 1 print error summary (ignore SW 13) SW 06 - 00 selects subtest NOTES: FFPAA0.BIN does not give error summary for test 11 when switches 7 and 13 equal a one. FFPB - 11/34 FP11-A part 2 ABSTRACT: To test the entire FP11-A run part 1, 2 and 3. Run the tests in sequence (first part 1 then 2-3). If you have no hardware switch register type "control G" to change the switches. The program prints the total number of passes completed and the total number of errors since the last end of pass message. Part 2 tests the following FP-11 instructions: ADDF add floating single precision numbers ADDD add floating double precision numbers SUBD subtract floating double precision numbers CMPD compare floating single precision numbers CMPF compare floating double precision numbers DIVD divide floating single precision numbers DIVF divide floating double precision numbers MULD multiply floating single precision numbers MULF multiply floating double precision numbers MODD multiply and integerize floating single p. MODF multiply and integerize floating double p. Some long floating point instructions can be interrupted (by BR from the UNIBUS) and started again (as if that instruction had never been started). This function can not be tested in the field. HARDWARE REQUIREMENTS: The test needs 15k of memory. OPERATING PROCEDURES: .R FFPB?? (200 normal start) The program prints its name, if there is no physical console it will ask for Switches = xxxxxx SWITCH SETTINGS: SW 14 = 1 loop on current test SW 13 = 1 inhibit error typeouts SW 12 = 1 inhibit T-bit trapping SW 11 = 1 inhibit iterations SW 10 = 1 ring bell on error SW 09 = 1 loop on error SW 08 = 1 loop on subtest specified in SW 06 - 00 SW 07 = 1 print error summary SW 06 - 00 selects subtest FFPC - 11/34 FP11-A part 3 ABSTRACT: To test the entire FP11-A run part 1, 2 and 3. Run the tests in sequence (first part 1 then 2-3). If you have no hardware switch register type "control G" to change the switches. The program prints the total number of passes completed and the total number of errors since the last end of pass message. Part 3 tests a lot of different floating point instructions, some of them with all possible source and destination modes. The result of the hardware floating point module is compared against the correct result written into the diagnostic. If Switch 12 = 0 then each program will run with trace traps on every other pass. First pass will not enable trace traps. Switch 12 = 1 disables T-bit trap. Some long floating point instructions can be interrupted (by BR from the UNIBUS) and started again (as if that instruction had never been started). This function can not be tested in the field. HARDWARE REQUIREMENTS: The test needs 15k of memory. OPERATING PROCEDURES: .R FFPC?? (200 normal start) The program prints its name, if there is no physical console it will ask for Switches = xxxxxx SWITCH SETTINGS: SW 15 = 1 halt on error SW 14 = 1 loop on current test SW 13 = 1 inhibit error typeouts SW 12 = 1 inhibit T-bit trapping SW 11 = 1 inhibit iterations SW 10 = 1 ring bell on error SW 09 = 1 loop on error SW 08 = 1 loop on subtest specified in SW 06 - 00 SW 07 = 1 print error summary SW 06 - 00 selects subtest NOTES: FFPCA0 Subtest #6 & #7 overlay data table with 177777 FKKA - 11/34 cache test ABSTRACT: It is a 12k program, tests module M8268. It uses the line clock (60/50 Hz.) for time measurement (memory location 176 = 0 is 60 Hertz, 1 is 50 Hertz). 124k of memory is needed for complete checkout of the TAG section in the cache (+ memory management). For DMA test you need a UNIBUS Exerciser box. Tests that all 4 cache control registers can be read writes and reads back each bit of all 4 registers. all HIT bits after a hit. the cache datapath and RAM chips with a pattern (rotating 1's in 0's). the cache flush feature the cache parity error logic that the I/O page is not cached the address path and TAG field with patterns the cache bypass mode that a DMA write invalidates cache (the UNIBUS Exerciser is needed to perform the DMA's) ........ and so on ........ OPERATING PROCEDURES: .R FKKA?? (200 normal start) The program prints its name, expected run time and enters the command mode by prompting : "CACHE=>" Valid commands are: LOT loop on test in error CLOT cancel LOT LOE loop on error (this is a close error loop) CLOE cancel LOE HOE halt on error CHOE cancel HOE IER inhibit error printout CIER cancel IER LST xxx loop on selected test xxx = test number CLST cancel LST RUN starts the test "^C" stops the test and returns to command mode Example: LST 121 will execute all tests before 121 and will loop on this test after. NOTES: FKKAA0.BIN failed with MS11-L memory and 50 Hz. FKTG - 11/34 instruction I/O exerciser ABSTRACT: This diagnostic and FKTH replace the obsolete diagnostics FKTA, FKTB, FKTC, FKTD and FKTF Memory Management. This is an overall check of the CPU, MEMORY MANAGEMENT in USER and KERNEL mode and up to 124k words of memory. For that it uses peripherals like a RK11-RK05, it writes data to the entire disk and verifies it by a write check. The power fail routine is not implemented. OPERATING PROCEDURES: .L FKTGC0 Set the desired option switches in memory location 174. Set the desired Switch Register (or if not available memory location 174). Load start address 200 and start. Restart address is 310 to keep the switch settings. The switches set before startup determine the wau in which memory is mapped and exercised. ERROR REPORTING: 3 words are printed : virtual PC+2 of error; the PSW at this time; the top 12 bits of 18 bit address of the memory bank being currently used. SWITCH SETTINGS: SOFTWARE SWITCHES (memory location 174 (normal 000 000)) BIT 00 = 1 disable memory management BIT 01 = 1 inhibit use of USER MODE BIT 02 = 1 inhibit test the 4k bank as 32k virtual BIT 05 = 1 inhibit variable memory expansion HARDWARE SWITCHES (memory location 176 if no SW REG) SW 15 = 1 halt on error SW 14 = 1 scope loop SW 13 = 1 inhibit print out SW 12 = 1 inhibit trace trapping SW 11 = 1 inhibit iteration SW 10 = 1 inhibit processor test These switches are only read at start of the test SW 07 = 1 use line printer SW 06 = 1 test TC11 DECtape SW 05 = 1 test RF11 disk SW 04 = 1 test LINE CLOCK SW 03 = 1 test RK11 disk SW 00 = 1 inhibit TTY output NOTES: FKTGA0.BIC was not chainable under XXDP+ FKTGB0.BIC does not address SWR correctly and no errors are printed FKTH - 11/34 memory management ABSTRACT: This is the MEMORY MANAGEMENT logic test using a "bottom-up" approach starting with the smallest segment and building up to cover all of the logic. The test is able to recover from a power fail if your system has core memory or MOS with battery backup. Only the R0 to R6 and SW register contents will be saved and recovered, not the memory management registers. Program starts at the beginning again. Starting with pass 3 every other pass will exercise the trace bit trapping (pass 3 then 5, 7, 9 ...) It prints "END OF PASS #??". OPERATING PROCEDURES: .R FKTH?? (200 normal start) SWITCH SETTINGS: Set the switches before program start SW 15 = 1 halt on error SW 14 = 1 loop on test SW 13 = 1 inhibit error print out SW 12 = 1 inhibit trace trapping SW 11 = 1 inhibit iteration SW 10 = 1 bell on error SW 09 = 1 loop on error SW 08 = 1 loop on test in SW 7 - 0 If your system has no hardware switch register use memory location 176 as the software switch register. Type "control G" to change the switches during testing. SW 07 - SW 00 selects subtest for SW 08. NOTES: FKTHA0.BIN lacked complete testing of non-resident abort logic.