JKDA - 11/23, 11/24 memory management ABSTRACT: This program was designed using a "bottom up" approach starting with the smallest segment of MEMORY MANAGEMENT logic possible and building up to cover all the logic. The program begins by testing some of the internal CPU data and address path and address detection logic, then works outward through the MEMORY MANAGEMENT registers. Then 18-bit and 22-bit mode relocation is tested (physical memory locations within 16k) followed by the testing of the abort and status segments of the logic. Finally, checks of special abort sequences and the MFPI / MTPI instructions are done. It will exercise T-bit trapping on every other pass starting with pass 3 then 5,7,9... unless inhibited. It will test 22-bit relocation "wraparound" to address 000000 with virtual address 111400 and PAR4 177664. HARDWARE REQUIREMENTS: The test needs 16k to run. SOFTWARE: This test assumes that the CPU test JKDB?? is running. OPERATING PROCEDURES: 200 normal start The test prints: CJKDAD0 KTF11-AA MMU DIAG. SWR = 000000 NEW = ERROR REPORTING: It will print the ERRPC, the TEST # and a nice error description. SWITCH SETTINGS: Use ^G to change the software switch register SW 15 =1 halt on error SW 14 =1 loop on test SW 13 =1 inhibit error printouts SW 12 =1 inhibit trace trapping SW 11 =1 inhibit iteration SW 10 =1 ring bell on error SW 09 =1 loop on error SW 08 =1 loop on test in SW <7-0> NOTES: JKDAA0.BIC Subroutine handling error. JKDAB0.BIC No code for line clock interrupts, needs corrections for multitester support. JKDAC0.BIC Needs update mainly for the 11/24. JKDB - 11/23, 11/24 CPU test ABSTRACT: This program contains three parts CPU, TRAP and EIS tests. In the first and second parts, the program will halt on errors, in part three, the EIS test, when an error is detected, the ERROR-PC and TEST-# will be typed then the program will continue execution. Part 1 the CPU checks out the basic PDP11 instructions in every addressing mode with various data patterns. Part 2 tests all trap instructions, trap overflow conditions R6, interrupts, the reset and wait instruction. Part 3 tests the EXTENDED INSTRUCTION SET, the ASH, ASHC, MUL and DIV instruction. HARDWARE REQUIREMENTS: The test needs 16k of memory. OPERATING PROCEDURES: 200 normal start 1024 restart address The test prints: CJKDBD0 DCF11-AA DIAGNOSTIC ERROR REPORTING: The diagnostic responds to errors in part 1 and 2 by storing certain information in memory and halting the processor. This information can be used by the operator to identify the error. For more infromation refer to your microfiche library. SWITCH SETTINGS: The initial contents of loc 176 is 000000, the user may preset this location before starting the program. You can do this by halting the CPU (use halt switch) deposit a 1 into 176 : @176/000000 1 examine 176 : @176/000001 proceed @P SW 15 =1 halt on error (part 3 only) SW 13 =1 inhibit error typeout (part 3 only) SW 01 =1 CIS chip set present SW 00 =1 skip trap test NOTES: JKDBA0.BIC Test is changing baudrate of DLV11 or DLV11-F with programmable baud rate. JKDBB0.BIC Test does not run with line clock enabled. JKDBC0.BIC Test needs update mainly for the 11/24. JKDC - 11/23, 11/24 FPP part 1 ABSTRACT: The two programs JKDCB0 and JKDDB0 are designed to detect and report logic faults in the F-11 MMU and FPP chip set (because part of the FP microcode is in the MMU chip). The program prints the total number of passes completed and the total number of errors since the last end of pass message. If SW 12 is 0 the program will run with Trace-Traps on every other pass. First pass will not enable Trace Traps (pass 3, then 5,7,9...) This part 1 tests the following FP11 instructions : LDFPS STFPS CFCC SETF SETD SETI SETL STST LDF LDD STD ADDF ADDD SUBD CMPD CMPF DIVD DIVF MULD MULF MODD MODF HARDWARE REQUIREMENTS: The test needs 16k of memory. SOFTWARE: This test will assume that the basic CPU is faultless, to make sure run JKDBD0 CPU test. OPERATING PROCEDURES: 200 normal start The program prints its name, if there is no physical console it will ask for Switches = xxxxxx SWITCH SETTINGS: Use ^G to change the software switch register SW 15 =1 halt on error SW 14 =1 loop on current test SW 13 =1 inhibit error typeout SW 12 =1 inhibit T-bit trapping SW 11 =1 inhibit iterations SW 10 =1 ring bell on error SW 09 =1 loop on error SW 08 =1 loop on subtest specified in SW 06 - 00 SW 06 - SW 00 selects subtest NOTES: JKDCA0.BIC Corrections needed for manufacturing (for multitester support). JKDD - 11/23, 11/24 FPP part 2 ABSTRACT: The two programs JKDCB0 and JKDDB0 are designed to detect and report logic faults in the F-11 MMU and FPP chip set (because part of the FP microcode is in the MMU chip). The program prints the total number of passes completed and the total number of errors since the last end of pass message. If SW 12 is 0 the program will run with Trace-Traps on every other pass. First pass will not enable Trace Traps (pass 3, then 5,7,9...) This part 1 tests the following floating point instructions : STF STD STCFD STCDF CLRD CLRF NEGF NEGD ABSF ABSD TSTF TSTD NEGF ABSF TSTF LDFPS LDCIF LDCLF LDCID LDCLD HARDWARE REQUIREMENTS: The test needs 16k of memory. SOFTWARE: This test will assume that the basic CPU is faultless, to make sure run JKDBD0 CPU test. OPERATING PROCEDURES: 200 normal start The program prints its name, if there is no physical console it will ask for Switches = xxxxxx SWITCH SETTINGS: Use ^G to change the software switch register SW 15 =1 halt on error SW 14 =1 loop on current test SW 13 =1 inhibit error typeouts SW 12 =1 inhibit T-bit trapping SW 11 =1 inhibit iterations SW 10 =1 ring bell on error SW 09 =1 loop on error SW 08 =1 loop on subtest specified in SW 06 - 00 SW 06 - SW 00 selects subtest NOTES: JKDDA0.BIC Corrections needed for manufacturing (for multitester support). JKDE - 11/24 CPU-Board test ABSTRACT: This is a quick test of the 11/24 CPU - module M7133, checking the CPU and EIS, MMU, FPP (KEF11-AA), LTC and 2 SLU's (Serial Line Units). This is a GO-NOGO test for the 11/24 CPU board. It does not contain the capabilities of scope looping, error recovery nor printing error information. Error halts do indicate which device failed to allow the technician to determine which diagnostic to use to fix the board. HARDWARE REQUIREMENTS: CPU (DCF11-AA 2 chips) MMU (KTF11-AA 1 chip) FPP (KEF11-AA 1 chip) LTC (line clock) 28k of memory 2 Serial Line Units (standard) 2nd SLU must have turnaround connector OPERATING PROCEDURES: 200 normal start ERROR REPORTING: The program does not type any error reports; it just halts the CPU and the console prints the PC. You need the listing (microfiche) to determine in which subtest the program failed or run the option specific tests: JKDA?? , JKDB?? , JKDC?? , JKDD?? , ZDLD??. SWITCH SETTINGS: Memory location 176. Console SW in HALT position. @000176/000000 2 deposits a 2 into mem loc 176 @R7/025110 200 writes 200 into R7 @P proceed (console SW in CONT) The initial contents of loc 176 is 000000, the user may preset this location before starting the program. SW 05 : program clears bit if CIS is not on board program will set bit if CIS is on board SW 04 =1 inhibit testing of SLU 2 SW 03 =1 inhibit testing of LTC SW 02 =1 inhibit testing of SLU 1 SW 01 =1 inhibit testing of FPP SW 00 =1 inhibit testing of MMU NOTES: Nothing. JKDF - 11/24 SLU & LTC test ABSTRACT: This program tests both serial line units (SLU's) and the line time clock (LTC) on the M7133 module. The program detects from 85-95% of all stuck-at-0, stuck-at-1 faults. Error typeouts identify a function that failed and to what logical portion of the board it failed on. This test is basically a rewrite of the DL11-W diagnostic. Its main purpose is to provide scope looping for repair personnel. The ECHO test (start 204) reads a character from terminal, writes it back and reports any error. Type Ctrl C to stop the ECHO test. To change software switches (loc 176) type Ctrl G but as the test is setting the maintenance bit in the console DL11, type ^G during program typeouts at that time the maintenance bits is cleared. HARDWARE REQUIREMENTS: The test needs TURN-AROUND-JUMPER installed on SLU2. The test needs minimum 8k of memory. OPERATING PROCEDURES : 200 normal start 204 the ECHO test will be executed 210 starts the terminal output test The test will print: SWR = 000000 NEW = SWITCH SETTINGS: Use ^G to change the SWR when program is running SW 15 =1 halt on error SW 14 =1 scope loop SW 13 =1 inhibit error typeout SW 10 =1 inhibit error flag test SW 09 =1 loop on error SW 07 =1 disable SLU 2 data test SW 06 =1 inhibit line clock test SW 05 =1 inhibit all SLU tests (both SLU's) SW 04 =1 inhibit SLU 1 testing SW 03 =1 inhibit SLU 2 testing SW 02 unused NOTES: Nothing. JKDH - 11/24 CIS test ABSTRACT: This diagnostic verifies the KEF11-BA (CIS commercial instruction set) option which consists of six MOS-LSI control chips contained in three 40-pin hybrid carriers. All CIS instructions are chip partitioned, i.e. all the code for a particular instruction is contained on a particular control chip. The exception is that all CIS instructions must pass through the first CIS chip (control chip DC303-004). In virually all cases, fault isolation is to the CIS chip level. HARDWARE REQUIREMENTS: The test needs 24k of memory and Memory Management and the first CIS chip DC303-004 must be installed. Any of the other CIS chips may be present. OPERATING PROCEDURES: 200 normal start The test prints: SWR = 000000 NEW = ERROR REPORTING: An error-typeout gives the ERROR-PC, the control chip number and what kind of failure occurred. The control chip number looks like 23-*04 ..., the * signifies the REV. level of the chip. The last two digits distinguishes one CIS chip from another. The part numbers for the hybrid assemblies are: 5700002-00 chips 23-*04 & 23-*06 5700003-00 chips 23-*05 & 23-*07 5700004-00 chips 23-*08 & 23-*09 SWITCH SETTINGS: Use ^G to change the software SW register SW 15 =1 halt on error SW 14 =1 scope loop SW 13 =1 inhibit error typeout SW 12 =1 not used SW 11 =1 inhibit subtest iteration SW 07 =1 Memory Management always disabled SW 06 =1 Memory Management always enabled SW 05 =1 test CIS control chip 9 (DC303-009) SW 04 =1 test CIS control chip 8 (DC303-008) SW 03 =1 test CIS control chip 7 (DC303-007) SW 02 =1 test CIS control chip 6 (DC303-006) SW 01 =1 test CIS control chip 5 (DC303-005) SW 00 =1 test CIS control chip 4 (DC303-004) Note: if SW 05-00 are all zero (default mode) then the diagnostic will test all six CIS chips. NOTES: Nothing.