JKDA - 11/23, 11/24 memory management ABSTRACT: This program was designed using a "bottom up" approach starting with the smallest segment of MEMORY MANAGEMENT logic possible and building up to cover all the logic. The program begins by testing some of the internal CPU data and address path and address detection logic, then works outward through the MEMORY MANAGEMENT registers. Then 18-bit and 22-bit mode relocation is tested (physical memory locations within 16k) followed by the testing of the abort and status segments of the logic. Finally, checks of special abort sequences and the MFPI / MTPI instructions are done. It will exercise T-bit trapping on every other pass starting with pass 3 then 5,7,9... unless inhibited. It will test 22-bit relocation "wraparound" to address 000000 with virtual address 111400 and PAR4 177664. HARDWARE REQUIREMENTS: The test needs 16k to run. SOFTWARE: This test assumes that the CPU test JKDB?? is running. OPERATING PROCEDURES: 200 normal start The test prints: CJKDAD0 KTF11-AA MMU DIAG. SWR = 000000 NEW = ERROR REPORTING: It will print the ERRPC, the TEST # and a nice error description. SWITCH SETTINGS: Use ^G to change the software switch register SW 15 =1 halt on error SW 14 =1 loop on test SW 13 =1 inhibit error printouts SW 12 =1 inhibit trace trapping SW 11 =1 inhibit iteration SW 10 =1 ring bell on error SW 09 =1 loop on error SW 08 =1 loop on test in SW <7-0> NOTES: JKDAA0.BIC Subroutine handling error. JKDAB0.BIC No code for line clock interrupts, needs corrections for multitester support. JKDAC0.BIC Needs update mainly for the 11/24. JKDB - 11/23, 11/24 CPU test ABSTRACT: This program contains three parts CPU, TRAP and EIS tests. In the first and second parts, the program will halt on errors, in part three, the EIS test, when an error is detected, the ERROR-PC and TEST-# will be typed then the program will continue execution. Part 1 the CPU checks out the basic PDP11 instructions in every addressing mode with various data patterns. Part 2 tests all trap instructions, trap overflow conditions R6, interrupts, the reset and wait instruction. Part 3 tests the EXTENDED INSTRUCTION SET, the ASH, ASHC, MUL and DIV instruction. HARDWARE REQUIREMENTS: The test needs 16k of memory. OPERATING PROCEDURES: 200 normal start 1024 restart address The test prints: CJKDBD0 DCF11-AA DIAGNOSTIC ERROR REPORTING: The diagnostic responds to errors in part 1 and 2 by storing certain information in memory and halting the processor. This information can be used by the operator to identify the error. For more infromation refer to your microfiche library. SWITCH SETTINGS: The initial contents of loc 176 is 000000, the user may preset this location before starting the program. You can do this by halting the CPU (use halt switch) deposit a 1 into 176 : @176/000000 1 examine 176 : @176/000001 proceed @P SW 15 =1 halt on error (part 3 only) SW 13 =1 inhibit error typeout (part 3 only) SW 01 =1 CIS chip set present SW 00 =1 skip trap test NOTES: JKDBA0.BIC Test is changing baudrate of DLV11 or DLV11-F with programmable baud rate. JKDBB0.BIC Test does not run with line clock enabled. JKDBC0.BIC Test needs update mainly for the 11/24. JKDC - 11/23, 11/24 FPP part 1 ABSTRACT: The two programs JKDCB0 and JKDDB0 are designed to detect and report logic faults in the F-11 MMU and FPP chip set (because part of the FP microcode is in the MMU chip). The program prints the total number of passes completed and the total number of errors since the last end of pass message. If SW 12 is 0 the program will run with Trace-Traps on every other pass. First pass will not enable Trace Traps (pass 3, then 5,7,9...) This part 1 tests the following FP11 instructions : LDFPS STFPS CFCC SETF SETD SETI SETL STST LDF LDD STD ADDF ADDD SUBD CMPD CMPF DIVD DIVF MULD MULF MODD MODF HARDWARE REQUIREMENTS: The test needs 16k of memory. SOFTWARE: This test will assume that the basic CPU is faultless, to make sure run JKDBD0 CPU test. OPERATING PROCEDURES: 200 normal start The program prints its name, if there is no physical console it will ask for Switches = xxxxxx SWITCH SETTINGS: Use ^G to change the software switch register SW 15 =1 halt on error SW 14 =1 loop on current test SW 13 =1 inhibit error typeout SW 12 =1 inhibit T-bit trapping SW 11 =1 inhibit iterations SW 10 =1 ring bell on error SW 09 =1 loop on error SW 08 =1 loop on subtest specified in SW 06 - 00 SW 06 - SW 00 selects subtest NOTES: JKDCA0.BIC Corrections needed for manufacturing (for multitester support). JKDD - 11/23, 11/24 FPP part 2 ABSTRACT: The two programs JKDCB0 and JKDDB0 are designed to detect and report logic faults in the F-11 MMU and FPP chip set (because part of the FP microcode is in the MMU chip). The program prints the total number of passes completed and the total number of errors since the last end of pass message. If SW 12 is 0 the program will run with Trace-Traps on every other pass. First pass will not enable Trace Traps (pass 3, then 5,7,9...) This part 1 tests the following floating point instructions : STF STD STCFD STCDF CLRD CLRF NEGF NEGD ABSF ABSD TSTF TSTD NEGF ABSF TSTF LDFPS LDCIF LDCLF LDCID LDCLD HARDWARE REQUIREMENTS: The test needs 16k of memory. SOFTWARE: This test will assume that the basic CPU is faultless, to make sure run JKDBD0 CPU test. OPERATING PROCEDURES: 200 normal start The program prints its name, if there is no physical console it will ask for Switches = xxxxxx SWITCH SETTINGS: Use ^G to change the software switch register SW 15 =1 halt on error SW 14 =1 loop on current test SW 13 =1 inhibit error typeouts SW 12 =1 inhibit T-bit trapping SW 11 =1 inhibit iterations SW 10 =1 ring bell on error SW 09 =1 loop on error SW 08 =1 loop on subtest specified in SW 06 - 00 SW 06 - SW 00 selects subtest NOTES: JKDDA0.BIC Corrections needed for manufacturing (for multitester support).