VKAA - 11/03 Basic Instr. test ABSTRACT: This program tests the LSI-11 basic instruction set in all modes. Trap type instructions are not tested. Power fail is supported. HARDWARE REQUIREMENTS: LSI-11(2) standard computer 4KW memory OPERATING PROCEDURES: Disable line time clock Load address 200 Start An END PASS message is printed RUN TIME: First pass less than 1 sec. Other passes less than 20 sec. SOFTWARE: This test runs stand alone. NOTES: On error the test may halt or print a message. VKAB - 11/03 EIS Instr. test ABSTRACT: This program tests the LSI-11 EIS instruction set (ASH, ASHC, MUL, DIV) using R0-R5. Power fail is supported. HARDWARE REQUIREMENTS: LSI-11(2) with the EIS/FPU chip inserted. 4KW memory, console. OPERATING PROCEDURES: Disable the line time clock Load address 200 Start An END PASS message is printed SWITCH SETTINGS: All zero for worst case. SW 15 =1 halt on error SW 13 =1 inhibit error printout RUN TIME: First pass less than 5 sec. Other passes less than 50 sec. SOFTWARE: This test runs stand alone. NOTES: On error the program may halt or print an error message. VKAC - 11/03 FIS Instr. test ABSTRACT: This program tests the LSI-11 floating point instruction set (FADD, FSUB, FMUL, FDIV). Power fail is supported. HARDWARE REQUIREMENTS: LSI-11(2) with the EIS/FIS chip inserted. 4KW memory, console. OPERATING PROCEDURES: Disable the line time clock Load address 200 Start SWITCH SETTINGS: SWR all zero for worse case. An END PASS message will be printed. SR 08 =1 loop on tst in SR <07 - 00> SR 09 =1 loop on error SR 10 =1 bell on error SR 11 =1 enable subtest iteration SR 12 =1 inhibit trace trapping SR 13 =1 inhibit error print out SR 14 =1 scope loop SR 15 =1 halt on error RUN TIME: Less than 30 sec. per pass. SOFTWARE: This program runs stand alone. NOTES: On error the program may halt or print an error message. VKAD - 11/03 TRAP test ABSTRACT: This is a test of all operations and instructions that cause traps, oddities of R6, interrupts, the reset and wait instructions. Power fail is supported. HARDWARE REQUIREMENTS: LSI-11(2), 4KW memory, console. OPERATING PROCEDURES: Disable the line time clock Load address 200 Start SWITCH SETTINGS: SWR (not standard, loc. 422) all zero for worse case. SR 01 =1 test I/O devices in area 160000 - 167777 SR 02 =1 suppress testing DIS/EIS 076030 - 076057 SR 03 =1 suppress testing opcodes 170000 - 177777 SR 04 =1 suppress testing opcodes 075400 - 076777 SR 05 =1 suppress END PASS message SR 06 =1 suppress testing EIS/FIS 070000 - 075037 RUN TIME: Less than 8 sec. for first pass. Other passes less than two mnutes. SOFTWARE: This program runs stand alone. NOTES: All errors cause a halt !! VKAH - 11/03 LSI-11 4k System Exerciser ABSTRACT: This tests the processors ability to operate peripherals in interrupt mode. Enable the line clock. It can run in as little as 4k words of memory. It runs an instruction test while peripherals interrupt the CPU. It tests up to 28k when relocation (SW9) is eanbled. The test can be stopped by typing control-C, the switches can be changed (@176/xxxxxx yyyyyy ) and the program continued by typing "P". Power fail is supported for systems with core or BBU. To run the low speed paper tape reader, a binary tape with a binary pattern of 000-377 is needed. OPERATING PROCEDURES: .L VKAH?? - halt the CPU, set the switches. Default switches : all I/O devices are disabled. If I/O devices selected : - make sure for the Floppy scratch diskettes installed (RX01 only) - for the DRV11 test cable (BC08R) is installed - @200G. ERROR REPORTING: It will print the PC, PSW and Return. SWITCH SETTINGS: Software switch register: memory location 176. Dynamic switch settings SW 15 =1 100 000 Halt on error SW 14 =1 040 000 Loop on subtest SW 13 =1 020 000 Inhibit error printout SW 12 =1 010 000 Inhibit T-Bit trapping SW 11 =1 004 000 Inhibit subtest iteration SW 10 =1 002 000 Inhibit processor instruction test SW 09 =1 001 000 Inhibit instruction test relocation SW 08 =1 000 400 Restart test on error) SW 07 =1 000 200 Inhibit "END OF PASS" printout Static switch settings (change before @200G) SW 06 =1 000 100 Inhibit TTY low speed reader test SW 05 =1 000 040 Inhibit line printer test SW 04 =1 000 020 Inhibit DRV11 parallel line unit test SW 03 =1 000 010 Inhibit EIS/FIS test SW 02 =1 000 004 Inhibit console output test SW 01 =1 000 002 Inhibit floppy unit 1 test (RX01 only) SW 00 =1 000 001 Inhibit floppy unit 0 test (RX01 only) RUN TIME: Time for one pass varies from 50 seconds with no I/O to 7.5 minutes with all I/O devices enabled. NOTES: A0 1. Software switch register is incorrectly set to 114177 instead 115117 (bit 9 inhibit test reloc.) as default. 2. The diagnostic checks for a hardware switch reg and fails at 1370. VKAI - 11/03 DIBOL Instr. test part 1 ABSTRACT: This test verifies operation of the DIBOL move and string instructions (MOVC, MOVRC, CMPC, LOCC, SKP, SCANC, SPANC). Check that each instruction is interuptable using the SLU. Power fail is supported. HARDWARE REQUIREMENTS: LSI-11(2) with DIBOL microms. 4 KW memory, console. OPERATING PROCEDURES: Disable the line time clock Load address 200 Start SWITCH SETTINGS : SWR all zero for worse case. SR 07 =1 inhibit interruptability test SR 08 =1 loop on tst in SR <05 - 00> SR 09 =1 loop on error SR 12 =1 inhibit trace trap SR 13 =1 inhibit error type out SR 14 =1 scope loop SR 15 =1 halt on error RUN TIME: Between 10 and 30 seconds depending on switch settings. SOFTWARE: This test runs stand alone. NOTES: The test attempts to always print an error message. VKAJ - 11/03 DIBOL Instr. test part 2 ABSTRACT: This test verifies the arithmetic instructions of the LSI-11 DIBOL instruction set (ADDN, SUBN, CMPN, CVTNL). Power fail is supported. HARDWARE REQUIREMENTS: LSI-11(2) with DIBOL microms. 4 KW memory, console. OPERATING PROCEDURES: Disable the line time clock Load address 200 Start SWITCH SETTINGS: SWR all zero for worse case. SR 07 =1 inhibit interruptability test SR 08 =1 loop on tst in SR <05 - 00> SR 09 =1 loop on error SR 12 =1 inhibit trace trap SR 13 =1 inhibit error type out SR 14 =1 scope loop SR 15 =1 halt on error RUN TIME: Between 10 and 30 seconds depending on switch settings. SOFTWARE: This test runs stand alone. NOTES: The test attempts to always print an error message. VKAL - 11/03 TRAP test part 2 (30k+FIS) ABSTRACT: This program is a copy of VKADB? with minor changes. The changes enable the program to run in a 30k memory system. The program defaults to running with "FIS" option. This tests all operations and instructions causing traps, oddities of R6, Interrupts, the reset and wait instruction. Power fail is supported for systems with core memory or BBU (Battery Back Up). HARDWARE REQUIREMENTS: A minimum of 4 kW of memory is required. OPERATING PROCEDURES: Disable the line time clock. .L VKAL?? - halt the CPU (witch switch) - @422/000000 xxxxxx put new value in . - Set the switches for the options you do not have. - @200G. ERROR REPORTING: All errors cause a halt. SWITCH SETTINGS: Software switch register: memory location 422. SW 06 =1 000 100 suppress testing EIS/FIS instructions SW 05 =1 000 040 suppress "END PASS" message SW 04 =1 000 020 supp. testing OP codes 075400-076777 SW 03 =1 000 010 supp. testing OP codes 170000-177777 SW 02 =1 000 004 supp. testing DIS/EIS 076030-076057 EIS/FIS = floating point option DIS/EIS = Dibol instruction set RUN TIME: First pass needs about 8 seconds. NOTES: A0 Test 73 fails at location 13142 because the default value of FIS testing is inverted. Patch loc 562 from 1403 to 1003. This will bring the test up to patch level A1. ZKMA - 11/03 Memory test (any PDP-11) ABSTRACT: This tests will test 0 - 124KW of MOS or core memory. Some subtests are worse for core and some for MOS, but all are always run. Power fail is supported. HARDWARE REQUIREMENTS: LSI-11 (or any PDP-11), 2KW of memory, console. OPERATING PROCEDURES: Disable the line time clock. Load address 200. Start SWITCH SETTINGS: Software switch register all zero for (28KW) worse case. SR 03 =0 beginning test number SR 04 =1 inhibit print out SR 05 =1 inhibit "PASS xx" print out SR 06 =1 inhibit memory sizing SR 07 =1 enable long galopping test SR 08 =1 type first failing bit error per 4KW SR 09 =1 inhibit program relocation SR 10 =1 halt after each subtest SR 11 =1 enable parity testing SR 12 =1 enable of above 28KW testing SR 13 =1 inhibit error print out SR 14 =1 loop in subtest SR 03-00 SR 15 =1 halt on error Control-C is supported, checked after subtest. RUN TIME: LSI-11 and 4KW : 100 sec. LSI-11 and 8KW : 5 min. SOFTWARE: The test runs stand-alone. NOTES: There are many more operating details, please refer to the listing.