.MCall	.Module
	.Module	SHANDL,06,<Supervisor library dispatcher>

; Copyright (c) 1998 by Mentec, Inc., Nashua, NH.
; All rights reserved
;
; This software is furnished under a license for use only on a
; single computer system and  may  be  copied  only  with  the
; inclusion of the above copyright notice.  This software,  or
; any other copies thereof, may not be provided  or  otherwise
; made available to any other person except for  use  on  such
; system and to one who agrees to these license  terms.  Title
; to  and  ownership of the software shall at all times remain
; in Mentec, Inc.
;
; The information in this document is subject to change without
; notice and should not be construed as a commitment by Digital
; Equipment Corporation, or Mentec, Inc.
;
; Digital and Mentec  assume  no  responsibility for the use or
; reliability of its software on equipment which is not supplied
; by Digital  or Mentec,  and listed  in the  Software  Product
; Description.
;17-Dec-89 JFW	initial type-in (derived from RSX TKB manual)
;02-Feb-90 JFW	change entry names for the condition code routines
;10-Dec-90 JFW	change return value from address to offset
;		add $OVRHS global to be used to call out from library
;		add $ASECT PSect to fill in vector
;14-Jan-91 JFW	delete .ASECT
;14-Jun-91 JFW	pad .ASECT to be 400 octal long to position $SHAND
;		psect just above CCB bit map.
;		delete $ASECT
.MCall	.Assume	.Br

.Library "SRC:EDTL"
.MCall	.ASTX

.SbTtl	Completion routine entry
.ASect
Base=.

.=0+Base			;Starts at Absolute 0!
	Bic	R0,R0		;Clear R0 (Completion routine entry)
	.ASTX

.SbTtl	CSM instruction vector

.=10+Base			;CSM vector is 010 in Supy I space !!!
	.Word	CSMSvr-Base	;enter service routine
				;NOTE: no PS in vector area

.SbTtl	Matching data for user stub library

.=12+Base			;match addresses in block 0 of user library
	.BlkW	1		;000012 Date in RT-11 format
	.BlkW	2		;000014 Time in RT-11 format
	.BlkW	2		;000022 Name of library in 2 RAD50 words
	.BlkW	1		;000024 Flags for lib attributes (share ...)
.=400+Base			;move $SHAND psect to 400
.SbTtl	CSM interrupt routine
; CSMSvr is entered via a 4 word transfer vector of the form:
;
;	MOV	#returntype,-(SP)
;	CSM	#routine
;
; The CSM instruction transfers control to the address contained in
; Supervisor I space virtual 10.  At this point the stack contents
; is the following:
;
;	  (SP) routine address
;	 2(SP) old PC
;	 4(SP) PS with cond codes cleared
;	 6(SP) return type address
;	10(SP) return address
;
; A routine address of 0 is a special case used to support return to
; Supervisor Mode from a debugger.  In this case the stack is the
; following:
;
;	  (SP) zero
;	 2(SP) PC from CSM (discard)
;	 4(SP) PS from CSM (discard)
;	 6(SP) super mode PC supplied by debugger
;	10(SP) super mode PS supplied by debugger
;

.PSect	$SHAND,GBL,I,RO
.Enabl	LSB

$OVRHS::			;Name used to load from library
CSMSvr:				;CSM interrupt routine
	Tst	@SP		;is the routine address = 0?
	Beq	10$		;yes, special debugger case
	Mov	6(SP),2(SP)	;set completion routine for return
	Add	#RetBas-Base,2(SP) ;And change to real address
	Jmp	@(SP)+		;and go to supervisor mode routine

10$:				;cleanup for debugger
	Cmp	(SP)+,(SP)+	;dump CSM residue from stack
	.Br	$SRTI		;and return

.SbTtl	Return entry point
;
; This entry point performs the necessary stack management to allow
; an RTI from super mode to either super or user mode.  In this case
; the stack is the following:
;
;	 (SP) PC
;	2(SP) PS
;
$SRTI::	Tst	2(SP)		;returning from U or S mode?
	Br	90$		;join common code
.SbTtl	$CCALL	- Return all condition codes
;
; Copy all condition codes to stacked PS.  Current stack:
;
;	 (SP) PS with completion code cleared
;	2(SP) completion routine address (discard)
;	4(SP) return address
;

Cond.C	=:	01		;carry bit
Cond.V	=:	02		;overflow bit
Cond.Z	=:	04		;zero bit
Cond.N	=:	10		;negative bit

RetBas:
.Assume	. EQ RetBas+<<<Cond.N*0>+<Cond.Z*0>+<Cond.V*0>+<Cond.C*0>>*2>
	Br	CCNil
.Assume	. EQ RetBas+<<<Cond.N*0>+<Cond.Z*0>+<Cond.V*0>+<Cond.C*1>>*2>
	Br	CCC
.Assume	. EQ RetBas+<<<Cond.N*0>+<Cond.Z*0>+<Cond.V*1>+<Cond.C*0>>*2>
	Br	CCV
.Assume	. EQ RetBas+<<<Cond.N*0>+<Cond.Z*0>+<Cond.V*1>+<Cond.C*1>>*2>
	Br	CCVC
.Assume	. EQ RetBas+<<<Cond.N*0>+<Cond.Z*1>+<Cond.V*0>+<Cond.C*0>>*2>
	Br	CCZ
.Assume	. EQ RetBas+<<<Cond.N*0>+<Cond.Z*1>+<Cond.V*0>+<Cond.C*1>>*2>
	Br	CCZC
.Assume	. EQ RetBas+<<<Cond.N*0>+<Cond.Z*1>+<Cond.V*1>+<Cond.C*0>>*2>
	Br	CCZV
.Assume	. EQ RetBas+<<<Cond.N*0>+<Cond.Z*1>+<Cond.V*1>+<Cond.C*1>>*2>
	Br	CCZVC
.Assume	. EQ RetBas+<<<Cond.N*1>+<Cond.Z*0>+<Cond.V*0>+<Cond.C*0>>*2>
	Br	CCN
.Assume	. EQ RetBas+<<<Cond.N*1>+<Cond.Z*0>+<Cond.V*0>+<Cond.C*1>>*2>
	Br	CCNC
.Assume	. EQ RetBas+<<<Cond.N*1>+<Cond.Z*0>+<Cond.V*1>+<Cond.C*0>>*2>
	Br	CCNV
.Assume	. EQ RetBas+<<<Cond.N*1>+<Cond.Z*0>+<Cond.V*1>+<Cond.C*1>>*2>
	Br	CCNVC
.Assume	. EQ RetBas+<<<Cond.N*1>+<Cond.Z*1>+<Cond.V*0>+<Cond.C*0>>*2>
	Br	CCNZ
.Assume	. EQ RetBas+<<<Cond.N*1>+<Cond.Z*1>+<Cond.V*0>+<Cond.C*1>>*2>
	Br	CCNZC
.Assume	. EQ RetBas+<<<Cond.N*1>+<Cond.Z*1>+<Cond.V*1>+<Cond.C*0>>*2>
	Br	CCNZV
.Assume	. EQ RetBas+<<<Cond.N*1>+<Cond.Z*1>+<Cond.V*1>+<Cond.C*1>>*2>
	.Br	CCAll
CCALL:				;handle NZVC
CCNZV:				;handle NZV, ignore C
CCNZC:				;handle NZC, ignore V
CCNZ:				;handle NZ, ignore VC
CCNVC:				;handle NVC, ignore Z
CCNV:				;handle NV, ignore ZC
CCNC:				;handle NC, ignore ZV
CCN:				;handle N, ignore ZVC
	Bpl	20$		;*C*V*Z*N* N clear?
CCZVC:				;handle ZVC, ignore N
CCZV:				;handle ZV, ignore NC
CCZC:				;handle ZC, ignore NV
CCZ:				;handle Z, ignore NVC
	Bne	30$		;*C*V*Z*   N set; Z clear?
CCVC:				;handle VC, ignore NZ
CCV:				;handle V, ignore NZC
	Bvc	40$		;*C*V*     NZ set; V clear?
	Bis	#Cond.N!Cond.Z!Cond.V,@SP ;*C* set NZV
	Br	80$		;*C* do carry

20$:
	Bne	60$		;*C*V*Z*   N clear; Z clear?
	Bvc	70$		;*C*V*     NZ clear; V clear?
	Bis	#Cond.Z!Cond.V,@SP ;*C* set ZV
	Br	80$		;*C* do carry

30$:
	Bvc	50$		;*C*V*	   N set; Z clear; V clear?
	Bis	#Cond.N!Cond.V,@SP ;*C* set NV
	Br	80$		;*C* do carry

40$:
	Bis	#Cond.N!Cond.Z,@SP ;*C* set NZ
	Br	80$		;*C* do carry

50$:
	Bis	#Cond.N,@SP	;*C* set N
	.Br	60$		;use Bvc 80$ as Br 80$, since V cleared by Bis

60$:
	Bvc	80$		;*C*V*     NZ clear; V clear?
	Bis	#Cond.V,@SP	;*C* set V
	Br	80$		;*C* do carry

70$:
	Bis	#Cond.Z,@SP	;*C* set Z
80$:	.Br	CCC		;join common code
.SbTtl	CCC - Return only Carry condition code
;
; copy only carry to stacked PS.  Current stack:
;
;	 (SP) PS with completion code cleared
;	2(SP) completion routine address (discard)
;	4(SP) return address
;
CCC:				;handle C, ignore NZV
				.Assume Cond.C EQ 1
	Adc	(SP)		;set carry bit if carry set
CCNIL:				;ignore all condition codes
	Mov	4(SP),2(SP)	;set up return address for RTT
	Mov	(SP)+,2(SP)	; and PS.
;>>>				.Assume	100000 EQ ??????
90$:
	Bpl	100$		;returning to S mode? (010000)
	Mov	#6,-(SP)	;pop three words
	Add	SP,@SP		;compute clear stack pointer
	Mtpi	SP		;fix up previous mode SP
100$:
	Rtt			;and return
.Dsabl	LSB
	.End