.MCALL .MODULE .MODULE RESHRD,VERSION=5,COMMENT=,IDENT=NO ; Copyright (c) 1998 by Mentec, Inc., Nashua, NH. ; All rights reserved ; ; This software is furnished under a license for use only on a ; single computer system and may be copied only with the ; inclusion of the above copyright notice. This software, or ; any other copies thereof, may not be provided or otherwise ; made available to any other person except for use on such ; system and to one who agrees to these license terms. Title ; to and ownership of the software shall at all times remain ; in Mentec, Inc. ; ; The information in this document is subject to change without ; notice and should not be construed as a commitment by Digital ; Equipment Corporation, or Mentec, Inc. ; ; Digital and Mentec assume no responsibility for the use or ; reliability of its software on equipment which is not supplied ; by Digital or Mentec, and listed in the Software Product ; Description. ;++ ; Facility: RESORC /H ; ; ; Edit Who Date Description of modification ; ---- --- ---- --------------------------- ; 001 WLD 19-JUL-90 Changes to recognize CPU types ; PDP-11/93 and PDP-11/94 ; 002 WLD 13-AUG-90 Fixed setting of the CC.FLU flag ; so that other bits in the CCR are ; preserved. ; 003 WLD 23-JAN-91 Change "Cycle" to "Hertz" -- ; result of "Commands Manual" review. ; Edit History: ; 001 George Stevens Overlaid version of RESORC. Created from RESORC ; Version 97 ;-- .NLIST .INCLUDE /SRC:RESPFX.MAC/ .LIST .SBTTL HRDWAR - List hardware configuration ;+ ; This routine lists the hardware configuration of the system. It does this ; as much as possible by using the configuration words of the monitor. ; If not possible, it uses a trap handler, as in the bootstrap. ;- ORIGIN RESHRD .ENABL LSB HRDWAR::.PRINT #CRLF ;Print a MOV $CNFG1(R5),R3 ;Get config word #1 MOV $CNFG2(R5),R4 ; and config word #2 BIT #,$SYSGN(R5) ;Is this an emulated environment? BEQ 10$ ;No, go do processor determination. PRINT EMUL8, CLR R2 ;Setup for entry to memory size print routine BR 60$ 10$: CALL $PDP11 ; Go get the processor type MOV R0,(PC)+ ; Save it for memory determination CPU:: .WORD 0 ; : CPU type word. ASL R0 ; Make it a word offset BGT 30$ ; Make sure it's in range 20$: CLR R0 ; Must be unknown 30$: ADD #PDPS,R0 ; Offset into table CMP R0,#PDPEND ; Is it out of range? BHIS 20$ ; Branch if so .PRINT @R0 ; Print the processor type FORMAT #BUFFER,< Processor> ;+ ; The following code compares CPU against 27 and 30 which are the two types ; for PRO325/PRO350 and PRO380. ;- CLR R2 ;Assume not a PRO CMP #PRO.380,CPU ; Is this a PC380? (value is 27) BEQ 40$ ; YES, GO PRINT ID ROM VALUE CMP #PRO.3XX,CPU ; Is this a PC325/350? (value is 30) BNE 50$ ; NO, SKIP ID ROM VALUE MOV #2048./64.,R2 ;Is a PRO, add 2K to memory, (real memory was ;reduced by 2K in BSTRAP to protect WIMP) ;(actually add 2K's worth of chunks) 40$: CALL PCID ; Yes, then add the ID ROM value. 50$: .PRINT #BUFFER ; Print the processor and ID. 60$: .TRPSET #AREA,#TRP1 ;Set up trap vector MOV $MEMPT(R5),R0 ;Point to low memory list ADD R5,R0 ;Get absolute address ADD $RAMSZ(R0),R2 ;Get memory size (32 wd blocks). CLC ;Don't let the carry get shifted in. ROR R2 ;Convert to 128 byte blocks. ASR R2 ;Convert to 256 byte blocks. ASR R2 ;Convert to 513 byte blocks. ASR R2 ;Finally....K bytes. FORMAT #BUFFER,<[D]KB of memory>,R2 .PRINT #BUFFER ;Output the amount of memory. TST FPAFG ;J11 with floating point accelerator? BEQ 80$ ;No, skip next BPL 70$ ;No FP accelerator PRINT ACCFPU, BR 90$ 70$: PRINT MICFPU, BR 90$ 80$: BIT #C1.FPU,R3 ;Got an FPU? BEQ 90$ ;Branch if not PRINT HWFPU, 90$: BIT #C2.EIS,R4 ;How about EIS? BEQ 100$ ;Branch if no PRINT EISET, 100$: BIT #C1.FPU,R3 ;Got an FPU? BNE 110$ ;Yes. Don't check for FIS MOV SP,R2 ;Point to stack (but don't destroy) MOV #40000,-(R2) ;We'll check for FIS by adding .5 to .5 CLR -(R2) ; MOV #40000,-(R2) ; CLR -(R2) ; FADD R2 ;Do a floating point add NOP ;One instruction delay for T11. BCS 110$ ;If C set, no FIS PRINT FIS, ;Tell the user 110$: BIT #C2.CIS,R4 ;Commercial instruction set? BEQ 120$ ;Branch if no PRINT CIS, ;Tell the user 120$: BIT #SY.RTE,$SYSGN(R5) ;Running under an emulator? BNE 140$ ;If yes, skip EAE check. .TRPSET #AREA,#TRPEAE ;Catch traps to 4 or 10 CLRB @#EAECS0 ;Check first possible location NOP ;Delay an instruction due to T11 BCC 130$ ;If no trap, then Carry clear .TRPSET #AREA,#TRPEAE ;Catch for second try CLRB @#EAECS1 ;Check second possible location NOP ;Delay an instruction due to T11 BCS 140$ ;If trapped, no EAE 130$: PRINT EAE, ;Tell the user ;+ ; Check if we are running under RTEM-11. If we are, the following ; checks are bypassed, since they return invalid information under ; the emulator: ; ; KT-11 Unit present check ; Parity memory check ; Cache memory ; PMI Memory ; VT11/VT48 Hardware ;- 140$: BIT #,$SYSGN(R5) ;Running under an emulator? BNE 230$ ;Branch if so, skip some checks. TST @#SR0 ;Check for KT11 NOP ;One instruction delay for T11. BCS 150$ ;Branch if no KT11 PRINT KT11, 150$: TST PDTFL ;PDT? BNE 190$ ;IF NE YES, SKIP PARITY CHECK CMP CPU,#SBC.21 ;Is this an SBC-11/21? BEQ 190$ ;If eq yes, skip parity check MOV #,R2 ;Point at the first parity CSR 160$: ADD #2,R2 ;Point to the next one TST @R2 ;Is it there? NOP ;One instruction delay for T11. BCS 165$ ;C bit set if not BIC #SGLERR,@R2 ;Clear the single error bit BIT #SGLERR,@R2 ;Is it still cleared? BNE 170$ ;Branch if not BIS #SGLERR,@R2 ;Set the single error bit BIT #SGLERR,@R2 ;Is it still set? BEQ 170$ ;Branch if not 165$: CMP R2,#PCSR16 ;Done yet? BLO 160$ ;Branch if not BR 175$ ;All done. 170$: PRINT PTYM, ;That's it. 175$: MOV #,R2 ;Point at the first parity CSR 180$: ADD #2,R2 ;Point to the next one CMP R2,#PCSR16 ;Done yet? BHI 190$ ;Branch if so BIC #SGLERR,@R2 ;Clear the single error bit BIT #SGLERR,@R2 ;Is it still cleared? BNE 180$ ;Branch if not BIS #SGLERR,@R2 ;Set the single error bit BIT #SGLERR,@R2 ;Is it still set? BEQ 180$ ;Branch if not PRINT ECCM, 190$: BIT #C2.CCH,R4 ;Got some cache? BEQ 200$ ;Branch if not PRINT CACH, 200$: TST PMIFG ;Do we have some PMI memory? BEQ 210$ ;Nope... PRINT PMIM, 210$: MOV #VT11,R2 ; Assume VT11 hardware display present TST @PAT3$ ; Is it? NOP ;One instruction delay for T11. BCS 230$ ; Take this branch if no TST @PAT4$ ; See if it's VT48 hardware NOP ;One instruction delay for T11. BCS 220$ ; Not if it takes this branch CMP CPU,#SBC.21 ;Is this an SBC-11/21? BEQ 230$ ;If eq yes, skip graphics check TST PDTFL ;PDT? ;002 BNE 230$ ;IF NE YES, SKIP GRAPHICS CHECK ;002 MOV #VT48,R2 ; It's a VS60. ;002 220$: .PRINT R2 ; Print one of the messages 230$: BIT #C1.CLCK,R3 ; Is there a clock? BEQ 260$ ; Branch if not MOV #60.,R2 ; Assume 60. cycle clock BIT #C1.CYCL,R3 ; Is it 50. cycle? BEQ 240$ ; Branch if not MOV #50.,R2 ; Set 50 cycle 240$: MOV #PCBLNK,R1 ;Assume no PC325/350 BIT #C2.PC,R4 ;Are we on a PC325/350? BEQ 250$ ;If not, branch BIT #C2.BUS,R4 ; BNE 250$ ;If not, branch MOV #PCCLK,R1 ;Get PC message 250$: FORMAT #BUFFER,<[D] Hertz System Clock [S]>, .PRINT #BUFFER 260$: BIT #C1.PCLK,R3 ;Got a user KW11-P? BEQ 270$ ;Branch if not PRINT KW11P, 270$: RETURN .DSABL LSB ;+ ; Subroutine to display the ID ROM on a PC300. ; ; On entry R0 -> formatting buffer. ; R2 saved ;- PCID:: MOV R1,-(SP) ; Save a few registers. MOV R2,-(SP) FORMAT R0,<, ID = > ; Add ID = text. MOV #PROID+12.,R1 ; R1 -> Pro ID register plus 12. 10$: MOV -(R1),R2 ; R2 = 2 digits. ASH #-4,R2 ; Shift into the low order bits. CALL PCIN ; enter the digit. MOV @R1,R2 ; R2 = Second digit. CALL PCIN ; Decode it. CMP #PROID,R1 ; All done? BLO 10$ ; No, continue. MOV (SP)+,R2 MOV (SP)+,R1 ; Yes, restore register. RETURN ; Return. PCIN: BIC #177760,R2 ; Strip all but the BCD digit. ADD #60,R2 ; Make it ASCII. MOVB R2,(R0)+ ; Store the digit. CLRB @R0 ; Clear out the next one RETURN ; and return .SBTTL $PDP11 - RT-11 Processor determination routine ;+ ; This routine determines the processor type. ; Outputs: ; R0 = a value indicating the processor type ; 0 = Unknown ; 1 = PDP 11/15 or 20 ; 2 = PDP 11/35 or 40 ; 3 = PDP 11/05 or 10 ; 4 = PDP 11/45 or 50 ; 5 = PDP 11/04 ; 6 = PDP 11/34 ; 10 = PDP 11/70 ; 11 = PDP 11/60 ; 12 = PDP 11/03, LSI 11 or LSI 11/2 ; 13 = PDP 11/44 (MFPT = 1) ; 14 = PDP 11/24 (MFPT = 3 though supposed to be 2!) ; 15 = PDP 11/23 (MFPT = 3) ; 16 = PDT 11/130 ; 17 = PDT 11/150 ; 20 = PDP 11/23 PLUS (MFPT = 3) ; 21 = SBC 11/21 (MFPT = 4) (T11) ; 22 = PDP 11/73A (MFPT = 5) (KDJ11-A) ; 23 = PDP 11/73B (MFPT = 5) (KDJ11-B, non-PMI) ; 24 = PDP 11/83 (MFPT = 5) (KDJ11-B w/PMI) ; 25 = PDP 11/84 (MFPT = 5) (KDJ11-B UNIBUS) ; 26 = reserved ; 27 = PC380 ; 30 = PC325, PC350, PC380 ; (what the heck?? - 27 vs. 30?) ; 31 = PDP 11/53 (MFPT = 4) (KDJ11-D) ; 32 = KXJ11-CA ; 33 = PDP 11/93 (KDJ11-E) ; 34 = PDP 11/94 (KDJ11-E) ; ;- .ENABL LSB $PDP11::.SAVRG ;Save non-volatile registers. CLR FPAFG ;Assume no J11 Floating Point ;+ ; ** PC325/PC350 ** ;- MOV #PRO.3XX,R0 ;Assume a PC3xx processor. BIT #C2.PC,$CNFG2(R5) ;Are we a PC? BEQ 1$ ;No, go on MOV R0,R1 MFPT ;What kind CMPB #MFPT23,R0 BEQ 11$ ;Its a 325,350 BR 13$ ;+ ; ** PDP 11/70 ** ;- 1$: MOV #PDP.70,R0 ;Assume we're running on an 11/70! BIT #C2.70,$CNFG2(R5) ;Are we? BNE 6$ ;Return if so. ;+ ; ** PDP 11/60 ** ;- .ASSUME PDP.60 EQ PDP.70+1 2$: INC R0 ;Select to assume an 11/60! BIT #C2.60,$CNFG2(R5) ;Was it? BNE 6$ ;Exit if so. ;+ ; ** LSI-11 or PDT-11 ** ;- .ASSUME PDP.LSI EQ PDP.60+1 3$: INC R0 ;Select to assume an LSI-11. BIT #C1.LSI,$CNFG1(R5) ;Is it an LSI or a PDT. BEQ 7$ ;No, then go try other types. MOV R0,-(SP) ;Save R0. .TRPSET #AREA,#TRP1 ;Set carry on traps. CLR R0 ;Set R0 for no return processing. MFPT ;Is is really an LSI? TST R0 ;Did the trap return 0? BEQ 4$ ;Yes, then it is an LSI or PDT. MOV (SP)+,R0 ;No, then must be an SBC 11/21. BR 7$ ;Carry on to other CPU types. 4$: .DSTATU #DSAREA,#SYSDEV ;Find out the boot device code. MOV (SP)+,R0 ;Restore R0. CMPB #PDT130,DSAREA ;Is this a PDT-11/130? BEQ 5$ ;Yes, then go select it. CMPB #PDT150,DSAREA ;A PDT-11/150? BNE 6$ ;No, then its an LSI so return. .ASSUME PDT.130 EQ PDP.LST+4 .ASSUME PDT.150 EQ PDT.130+1 INC R0 ;Yes, then select a PDT-11/150. 5$: ADD #4,R0 ;PDT code = LSI code + 4. INC PDTFL ;Remember that it is a PDT. 6$: RETURN ;General return point. ;+ ; Set up to determine processors which support MFPT. ;- 7$: MOV R0,R1 ;Save processor type flag. .TRPSET #AREA,#TRP4 ;All traps to the same line. MOV #21$,R5 ;On traps to 4 or 10 go to 21$. MFPT ;What are you? BIC #177400,R0 ;Don't care about the subcode. ;+ ; ** PDP 11/44 ** ;- .ASSUME PDP.44 EQ PDP.LSI+1 8$: INC R1 ;Assume this is an 11/44. CMPB #MFPT44,R0 ;Is this a PDP-11/44. BEQ 11$ ;Yes, then go exit. ;+ ; ** PDP 11/24 ** ;- .ASSUME PDP.24 EQ PDP.44+1 9$: INC R1 ;Assume an 11/24. CMPB #MFPT23,R0 ;F-11 processor? BNE 12$ ;No, then it isn't an 11/24. MOV #10$,R5 ;Check for 11/23 if we trap. CLR @#SWR ;Try to write to the switch register. BR 11$ ;Didn't trap so we're a ??, go exit. ;+ ; ** PDP 11/23 and PDP 11/23 PLUS ** ;- .ASSUME PDP.23 EQ PDP.24+1 10$: INC R1 ;Assume an 11/23. MOV #11$,R5 ;If we trap, then it is an 11/23. BIT #100,@#LKS ;RT-11 has the clock on. BEQ 11$ ;If 0 or we trap, its an 11/23. BIT #40,@#LKS ;Is the clock from an MXV-11B LCCR? BNE 11$ ;Yes, then it isn't an 11/23 plus! MOV #PLUS.23,R1 ;Clock is 1 so its an 11/23 plus. 11$: MOV R1,R0 ;General return, put type into R0. RETURN ;Go return to the caller. ;+ ; ** All other MFPT processors (SBC 11/21, PDP 11/73,74) ** ;- 12$: ADD #<21-MFPTT1>,R0 ;Calculate the type code. CMP #21,R0 ;Is this some type of KDJ11 .Assume MFPTT1+1 EQ MFPTJ1 BNE 13$ ;NO, its an SBC RETURN 13$: MOV #1,FPAFG ;Assume no accelerator MOV @#CMR,R1 ;Read the maintenance register BIT #CMR.FP,R1 ;Is there an accelorator? BEQ 14$ ;NO, there isn't NEG FPAFG ;Neg value says there is one 14$: BIT #C2.PC,$CNFG2(R5) ;Are we a PC? BEQ 15$ ;NO MOV #PRO.380,R0 ;Assume PRO 380 BIT #C2.KX,$CNFG2(R5) ;Are we a KXJ? BEQ 19$ ;NO MOV #PDP.KX,R0 ;Yes RETURN 15$: BICB #^C,R1 ;Mask out the subcode 7:4 CMPB #J11A,R1 ;How about a KDJ11A BNE 16$ RETURN ;Assume r0 = 22 16$: CMPB R1,#J11B ;KDJ11-B based machine? BEQ 17$ ;Yes, branch CMP #J11D,R1 ; 11/53 ? BNE 210$ ;BR IF NOT: MAY BE 11/93 OR 11/94. MOV #PDP.53,R0 ; Point to 11/53 RETURN 17$: CLR PMIFG ;Assume no PMI memory MOV @#PSW,-(SP) ;Save current priority BIS #340,@#PSW ;Before locking out interrupts BIS #CC.FLU,@#CCR ;;;Flush the cache NOP ;;;Flush a bit in hit/miss register NOP ;;; and another NOP ;;; and another NOP ;;; and another MOV @#HMR,R0 ;;;Get contents of hit/miss register MOV (SP)+,@#PSW ;;;Unlock interrupts BIT #77,R0 ;Were there any cache hits? BEQ 18$ ;Nope, so not PMI INC PMIFG ;Yes, indicate we have PMI 18$: BIT #1000,R1 ;Running on a unibus KDJ? BNE 20$ ;Yes, must be 11/84 (of some kind)... MOV #PDP73B,R0 ;Assume it's a normal 11/73B TST PMIFG ;Does machine have PMI memory? BEQ 19$ ;Nope... .ASSUME PDP.83 EQ PDP73B+1 INC R0 ;Yes, then 11/83 (code = 24) 19$: RETURN 20$: MOV #PDP.84,R0 ;11/84 RETURN 210$: CMPB R1,#J11E ;IS IT A PDP-11/93 OR PDP-11/94? BNE UNK ;BR IF NOT: NOT KDJ11-E. MOV #PDP.93,R0 ;TRY A PDP-11/93. BIT #1000,R1 ;QBUS OR UNIBUS? BEQ 220$ ;BR IF QBUS: PDP-11/93. MOV #PDP.94,R0 ;UNIBUS: PDP-11/94. 220$: RETURN UNK: CLR R0 ;UNKNOWN RETURN ;Go call the user. ;+ ; ** All other non-MFPT processors ** ;- 21$: .TRPSET #AREA,#TRP3 ;Set up traps to 4 and 10 CLR R4 ;Get the flag word MOV #22$,R5 ;And address to return to from trap MOV #1,R3 ;Set flag for 05 or 20 SXT R1 ;This will trap on 05 or 20 ROL R3 ;Must be 40 or 45 type SPL 0 ;This will trap if 34 or 40 ROL R3 ;Must be 45 or 50 BIS R3,R4 ;Set the flag word 22$: .TRPSET #AREA,#TRP4 ;Everything traps to same place now MOV #1,R3 ;Set up flag bit BIT R3,R4 ;Is it an 11/05 or 11/20 type? BEQ 27$ ;Branch if not MOV #28$,R5 ;Return to 28$ on trap TST @#177700 ;Trap if it's an 11/15 or 11/20 MOV #23$,R5 ;Return here on traps .MFPS ;Get the processor status on the stack MOV #25$,-(SP) ;Go here if RTT works RTT ;If it works, it's an 11/04 23$: MOV #24$,@SP ;Clean up the stack if not 11/04 RTI 24$: BIS #2,R4 ;Say that it's an 11/05 or 11/10 BR 28$ ;We're done 25$: BIS #4,R4 ;Set the bit 26$: BR 28$ ;And done 27$: CLC ;Make sure nothing in C bit ROL R3 ;Shift the flag BIT R3,R4 ;Is it a 34 or 40 type processor? BEQ 28$ ;Branch if not. It's an 11/45 MOV #28$,R5 ;We're done if we trap (11/40) MFPS -(SP) ;11/34 instruction (move from PSW) TST (SP)+ ;It's a 34. Clean stack BIS #4,R4 ; and set the bit. 28$: MOV R4,R0 ;Save the value RETURN .DSABL LSB .END