AC0 = %0
AC1 = %1
AC2 = %2
AC3 = %3
AC4 = %4
AC5 = %5

V.0	=: ^O<	0>
V.TR4	=: ^O<	4>
V.TR10	=: ^O< 10>
V.BPT	=: ^O< 14>
V.IOT	=: ^O< 20>
V.PWFL	=: ^O< 24>
V.EMT	=: ^O< 30>
V.TRAP	=: ^O< 34>
V.PET   =: ^O<114>
V.PIRQ	=: ^O<240>
V.FTRP  =: ^O<244>
V.MMU	=: ^O<250>

;
; Device vectors and registers
;

SWREG   =: ^O<177570>
DSPREG  =: ^O<177570>

; Clock

V.LTC	=: ^O<100>
LCCSR   =: ^O<177546>	; line clock

V.PTC	=: ^O<104>	; kw11p clock
PCCSR   =: ^O<172540>

; Console

V.TKB	=: ^O< 60>
V.TPS	=: ^O< 64>

TKS	=: ^O<177560>
TKB	=: ^O<177562>
TPS	=: ^O<177564>
TPB	=: ^O<177566>

HM.TKS	=: ^O<177060>
HM.TKB	=: ^O<177062>
HM.TPS	=: ^O<177064>
HM.TPB	=: ^O<177066>

V.HTKB	=: ^O<560>
V.HTPS	=: ^O<564>

; Line printer

LPS	=: ^O<177514>
LPB	=: ^O<177516>

MSVCSR	=: ^O<172100>

SLUBA	=: ^O<176500>		; KDJ11-E SLUs base address
SLUBV	=: ^O<300>		; base vector
SLUAA	=: ^O<176600>		; KDJ11-E SLUs alternate address
SLUAV	=: ^O<400>		; alternate vector

H$R0	=: ^O<177700>		; R0 bus address on some PDP-11
H$R1	=: ^O<177701>		; R1 bus address on some PDP-11
H$R2	=: ^O<177702>		; R2 bus address on some PDP-11
H$R3	=: ^O<177703>		; R3 bus address on some PDP-11
H$R4	=: ^O<177704>		; R4 bus address on some PDP-11
H$R5	=: ^O<177705>		; R5 bus address on some PDP-11
H$SP	=: ^O<177706>		; SP bus address on some PDP-11
H$PC	=: ^O<177707>		; PC bus address on some PDP-11

PCR	=: ^O<177520>		; Page Control Register on KDJ11-A

BCSR	=: ^O<177520>		; Control/Status Register on KDJ11-B ; EK-PDP94-MG-001_Sep90.pdf pg. 5-27
	CS.BRE =: ^O<100000>		; Battery backup reboot enanle (1 - battery backup voltage failed to maintain the system memory
					;                               0 - battery backup voltage maintained the system memory or
					;                                     there are no battery backup
	CS.PLS =: ^O<40000>		; DCOK is pulsed while the POK input remains asserted -
					;   system reboot was requested by the control panel switch
	CS.FIE =: ^O<20000>		; Force line clock interrupt enable.
	CS.DLR =: ^O<10000>		; Disable line clock register
	CS.CS1 =: ^O<4000>		; Clock select
	CS.CS0 =: ^O<2000>		; 00 - external BEVNT, 01 - on board 50 Hz, 10 - 60 Hz, 11 - 800 Hz
	CS.EHB =: ^O<1000>		; Enable HALT Break
	CS.SM  =: ^O<400>		; Enable standalone mode 
	CS.DW7 =: ^O<200>		; Disable 17773000 ROM windows
	CS.DW6 =: ^O<100>		; Disable 17765000 ROM windows
	CS.EEP =: ^O<40>		; 0 - ROM at 17765000, 1 - EEPROM at 17765000
	CS.EWE =: ^O<20>		; 1 - EEPROM write enabled
		;    10			; Not used, read as zero
	CS.GC2 =: ^O<4>			; Processor mastership
	CS.GC1 =: ^O<2>			; grant count
	CS.GC0 =: ^O<1>			; 000 - disabled, 001 - 0.4 mks, ..., 111 - 25.6 mks


PCRB	=: ^O<177522>		; Page Control Register on KDJ11-B ; EK-PDP94-MG-001_Sep90.pdf pg. 5-29

CDR	=: ^O<177524>		; J-11 configuration and display register; EK-PDP94-MG-001_Sep90.pdf pg. 5-30
;      -- SW1         - Console mode (1 - disable console)
;      -- SW2 SW3 SW4 - boot ROM mode
;      -- SW5         - force dialog mode
;      -- SW6 SW7 SW8 - console baud rate
	CD.DCN =: ^O<200>		; Disable console
	CD.DLG =: ^O<10>		; Force dialog
	CD.SP2 =: ^O<4>			; UART
	CD.SP1 =: ^O<2>			;   speed
	CD.SP0 =: ^O<1>			;     select

ADSR	=: ^O<177526>		; J-11 additional status register; EK-PDP94-MG-001_Sep90.pdf pg. 5-31
		; ^O<100000>
		; ^O<40000>
	AD.SS  =: ^O<20000>	; Serial select (0 - 176500/300, 1 - 176600/400)
	AD.SE  =: ^O<10000>	; Serial enable
		; ^O<4000>
		; ^O<2000>
		; ^O<1000>
	AD.TOY =: ^O<400>	; TOY communication
		; ^O<200>
		; ^O<100>
	AD.MS  =: ^O<40>	; Memory select  (0 - 0..2 mb, 1 - 0..4 mb)
	AD.ME  =: ^O<20>	; Memory enable
		; ^O<10>
		; ^O<4>
	AD.PMI =: ^O<2>		; Flag for PMI cycle (set by system)
		; ^O<1>

DCSR	=: ^O<177730>		; J-11 diagnostic controller status register; EK-PDP94-MG-001_Sep90.pdf pg. 5-49 UBA ctrl
	DC.NXM =: ^O<100000>		; Diagnostic nonexistent mempry error register
		; ^O<40000>
		; ^O<20000>
		; ^O<10000>
		; ^O<4000>
		; ^O<2000>
		; ^O<1000>
	DC.DM  =: ^O<400>		; Diagnostic mode
	DC.DON =: ^O<200>		; DNPR done
		; ^O<100>
		; ^O<40>
		; ^O<20>
	DC.BRD =: ^O<10>		; Unibus boot ROM at 17 773 000 disabled
	DC.DR1 =: ^O<4>			; Diagnostic data register selection
	DC.DR0 =: ^O<2>			; ...
	DC.DGO =: ^O<1>			; Diagnostic DATI GO

DDR	=: ^O<177732>		; J-11 diagnostic data register; EK-PDP94-MG-001_Sep90.pdf pg. 5-51

KMCR	=: ^O<177734>		; J-11 memory configuration register; EK-PDP94-MG-001_Sep90.pdf pg. 5-48


;177740	low error address register, EK-KB11C-TM-001_1170procMan.pdf pg. VI-4-18
;177742	high error address register, EK-KB11C-TM-001_1170procMan.pdf pg. VI-4-18

MSER	=: ^O<177744>		; Memory system error register, EK-KB11C-TM-001_1170procMan.pdf pg. VI-4-19
	MS.PE  =: ^O<100000>		; Parity error abort
	MS.PEH =: ^O<   200>		; Parity error high
	MS.PEL =: ^O<   100>		; Parity error low
	MS.PET =: ^O<    40>		; Parity error tag


CCR	=: ^O<177746>		; Cache Control Register, EK-KB11C-TM-001_1170procMan.pdf pg. VI-4-19
	CC.wTP =: ^O<2000>		; Write wrong parity
	CC.BP  =: ^O<1000>		; Cache bypass
	CC.FL  =: ^O< 400>		; Flush cache
	CC.EPA =: ^O< 200>		; Enable parity error abort
	CC.WWP =: ^O< 100>		; Write wrong parity
	CC.FM1 =: ^O<  10>		; Force miss bit 1
	CC.FM0 =: ^O<   4>		; Force miss bit 0
	CC.DM  =: ^O<   2>		; Diagnostic mode
	CC.DPI =: ^O<   1>		; Disable cache parity interrupt


CPUMR	=: ^O<177750>		; Maintenance register, EK-KB11C-TM-001_1170procMan.pdf pg. VI-4-21
	CM.B15 =: ^O<100000>		; User Boot bit 15 Address
	CM.B14 =: ^O< 40000>		; User Boot bit 14 Address
	CM.B13 =: ^O< 20000>		; User Boot bit 13 Address
	CM.B12 =: ^O< 10000>		; User Boot bit 12 Address
	CM.UBS =: ^O<  1000>		; Unibus system
	CM.FPA =: ^O<   400>		; Floating Point Accelerator present
	CM.ID3 =: ^O<   200>		; Module ID bit 3
	CM.ID2 =: ^O<   100>		; Module ID bit 2  On J11 - 0001
	CM.ID1 =: ^O<    40>		; Module ID bit 1
	CM.ID0 =: ^O<    20>		; Module ID bit 0
	CM.HLT =: ^O<    10>		; HALT enabling
	CM.PW1 =: ^O<     4>		; Power On bit 1 option  00 - PC from 24, PS from 26	01 - MicroODT, PS = 0
	CM.PW0 =: ^O<     2>		; Power On bit 0 option  10 - PC = 173000, PS = 0	11 - PC = USer Boot + "0000", PS = 0
	CM.POK =: ^O<     1>		; Power OK

CHMR	=: ^O<177752>		; Cache hit/miss register, EK-KB11C-TM-001_1170procMan.pdf pg. VI-4-21

;177754	Cache Data register (ρμ PDP-11/44)

;177760	System Size - Lower
;177762	System Size - Upper
;177764	System Id

CPUERR	=: ^O<177766>		; CPU Error Register
	CE.HLT =: ^O<200>		; Illegal HALT
	CE.ADR =: ^O<100>		; Address errkr
	CE.NXM =: ^O< 40>		; Non-Existing memory
	CE.IO  =: ^O< 20>		; I/O bus timeout
	CE.YSP =: ^O< 10>		; Yellow stack violation
	CE.RSP =: ^O<  4>		; Red stack violation

;177770	microbreak register, EK-KB11C-TM-001_1170procMan.pdf

PIRQ	=: ^O<177772>		; Program interrupt Request
	IR.PR7 =: ^O<100000>
	IR.PR6 =: ^O< 40000>
	IR.PR5 =: ^O< 20000>
	IR.PR4 =: ^O< 10000>
	IR.PR3 =: ^O<  4000>
	IR.PR2 =: ^O<  2000>
	IR.PR1 =: ^O<  1000>
	IR.PR0 =: ^O<   400>

;177774	Stack limit

PS	=: ^O<177776>
	PR0	=: ^O<0*40>
	PR1	=: ^O<1*40>
	PR2	=: ^O<2*40>
	PR3	=: ^O<3*40>
	PR4	=: ^O<4*40>
	PR5	=: ^O<5*40>
	PR6	=: ^O<6*40>
	PR7	=: ^O<7*40>

	ALT.RG	=: ^O<4000>
	K.MODE	=: ^O<0*40000>
	S.MODE	=: ^O<1*40000>
	U.MODE	=: ^O<3*40000>

	C.BIT 	=: ^O<1>